1. 1 EE244 Project Your Title EE244 – Fall 2000 Name 1 Name 2

2. 2 EE244 Project Power Considerations in ASIC Packaging for the Next Millennium EE244 – Fall 1999 Kevin Cao Yeh-Jiun Tung

3. 3 EE244 Project Outline Motivation Problem statement Prior work Investigative approach Results Summary Conclusions Future Work

4. 4 EE244 Project Example: Motivation: Why packaging and power together? Consumer demand for powerful portable devices (ASICs) As technology generation scales: –Chip speed  –Total chip area  –Total power   Increased demands on packaging (without the luxury of fan-cooling) So… will our PDA/cell-phone/wireless- web-browser meltdown in 2010?

5. 5 EE244 Project Problem statement 1.What is the problem that you are trying to solve? 2.What do you want to find out that the world doesn’t already know? 3.What would it mean for you to be successful – I.e. what is your hypothesis? 4. Could you be all wrong? e.g. optimizing where there is no difference e.g. problem (e.g. power dissipation) is somewhere else

6. 6 EE244 Project Prior Work 1.Describe prior work related to your project 2. How is this work relevant? 3. Does the prior work have any defficiencies? 4. How will your work differ?

7. 7 EE244 Project Investigative Approach 1.Describe the approach that you will use to resolve your key questions 2.Clearly define: –What you borrowed (that’s fine) –What you developed 3. What are the limits to your approach?

8. 8 EE244 Project Example - Investigative Approach 1.Estimate ASIC power for each future technology generation –use BACPAC model –determine ASIC performance 2.Determine packaging technology limitations (imposed by chip power) 3.Merge (1) & (2) to find power / performance limitations imposed by packaging for future technology generations

9. 9 EE244 Project Berkeley Advanced Chip PerformAnce Calculator (BACPAC)* “Bottom-up” approach –Transistor level –Logic level –System level System-level analysis –Logic and local wiring –Global Interconnect –Clock Distribution –I/O Drivers and Pads –On-Chip Memory * developed by D.Sylvester and K.Keutzer

10. 10 EE244 Project BACPAC – ASIC Modeling Larger internal Rent’s exponent (than  P’s) –reflects less efficient layout typical of ASICs Larger external Rent’s exponent –Models larger I/O count of ASICs 40% of transistors for on-chip memory Larger clock skew permissible than  P’s Lower silicon efficiency

11. 11 EE244 Project Results 1.What is the result of your research 2.Clearly define: –What you borrowed (that’s fine) –What you developed 3. What are the limits to your approach?

12. 12 EE244 Project Power Limitations Hand-held ASICs Hand-held ASIC P in   c-a < 100 o C Hand-held ASICs pose no problems for package power dissipation…  What about high- performance ASICs? Plastic Flip Chip Chip-Scale Packaging Wire bonding Ball grid array BACPAC predictions

13. 13 EE244 Project Power Limitations High-Performance ASICs High-Performance ASIC P in   c-a < 100 o C Packaging technology imposes limitations on high-performance ASICs  What is the effect on chip metrics? Plastic Flip Chip Chip-Scale Packaging Wire bonding Ball grid array BACPAC predictions

14. 14 EE244 Project Summary Summarize your results in an easy to understand way What are the key points? Graphics are always helpful

15. 15 EE244 Project Components Contributing to Power For typical high-performance ASIC 0.25 um 0.18 um0.13 um 0.10 um 0.07 um 0.05 um Technology Generation Percentage of total power

16. 16 EE244 Project Power Reduction Strategies * LevelStrategy Processing/ Transistor Reduce/multiple V dd, reduce geometry, reduce/multiple V t, reduce temperature Gate Static vs. dynamic CMOS, reversible logic (adiabatic gates), order transistor turn-on sequence for multiple fan- in gates Logic Reduce # of transistors within operation, reduce size of non-critical gates, asynchronous design RTL Choose adjacent state assignments for frequent state transitions Behavioral Shut down idle operators, choose lowest possible V dd, mixed V dd, use fast operators only critical paths Algorithmic Choose low-power algorithm * Adapted from R.San Martin and J.P. Knight, IEEE Design & Test of Computers, summer 1996

17. 17 EE244 Project Conclusion and Future Work What can we conclude (not just restate) about your project What are the strengths of your work? What are the deficiencies? What would you like to do in the future?

18. 18 EE244 Project Conclusion Current packaging technology will be sufficient for low-performance ASICs Packaging technology will severely limit ASIC performance in the future –Chip speed cannot exceed 1 GHz at 0.05  m technology even for best packaging technology (Ball Grid Array) Power optimization strategies must be implemented to reduce demands placed on packaging