1. Designing a Processor from the Ground Up to Allow Voltage/Reliability Tradeoffs Andrew Kahng (UCSD) Seokhyeong Kang (UCSD) Rakesh Kumar (Illinois) John Sartori (Illinois)

2. Timing Errors Power is a first-order design constraint Voltage scaling can significantly reduce power Voltage scaling may result in timing errors Operating Voltage

3. Research Questions How does a conventional processor behave when we fix frequency and scale down voltage? How can we reduce the voltage at which timing errors are observed? Reduce power while maintaining the same performance level

4. Limitation of Voltage Scaling At some voltage, circuit breaks down Voltage scaling must halt after only 10% scaling.

5. Limitation of Voltage Scaling Error Rate (%) Module1.0V0.9V0.8V0.7V0.6V0.5V lsu_dctl0.000.238.6029.4645.1354.90 lsu_qctl10.005.9410.8516.9916.5637.53 lsu_stb_ctl0.000.080.655.1911.7922.38 sparc_exu_div0.000.150.230.350.491.10 sparc_exu_ecl0.003.3110.9787.0888.9373.03 sparc_ifu_dec0.000.080.877.0915.2220.48 sparc_ifu_errdp0.00 9.21 sparc_ifu_fcl0.0010.5622.2550.0455.0656.95 spu_ctl0.00 1.302.9635.53 tlu_mmu_ctl0.000.010.020.060.140.19 What problems are caused by steep error degradation?

6. Problems with Steep Error Degradation Voltage scaling limited in traditional designs.

7. No power savings as error rate increases Traditional design  No reliability/power tradeoff Problems with Steep Error Degradation

8. Why do circuits fail catastrophically? Reliability/power tradeoffs enabled Allows switching between error tolerance techniques at different voltages/error rates Higher error rate  Lower power Problems with Steep Error Degradation

9. Reason for Steep Error Degradation Critical paths are bunched up in traditional designs.

10. Question… How can we change the slack distribution to achieve a graceful failure characteristic?

11. Power-optimized design: Reclaim excess timing slack Make slack distribution gradual by re-distributing slack between paths. Both gradual failure and low power can be achieved. Slack-optimized design: Optimize critical paths Design Objectives and Insight Optimize frequently exercised critical paths. De-optimize rarely exercised paths.

12. Positive SlackNegative Slack Slack Re-distribution Example 0.0 -0.1 Negative SlackPositive Slack Error Rate = 1%Error Rate = 25%

13. Proposed Design Flow Voltage Scaling  Path Optimization  Area Reduction Input: RTL description Output: Gradual slack design Objective: Minimize voltage for a given error rate over a range of error rates

14. Using fixed target results in over-optimization.Iterative optimization avoids unnecessary swaps. Iterative Optimization

15. Error Rate Forecasting

16. Functional simulation Cadence NC Verilog – Gate-level simulation Library characterization Cadence SignalStorm – Synopsys Liberty generation for each voltage Slack Optimization C++ with Synopsys PrimeTime interface ECO P&R Cadence SOCEncounter – Placement and Routing Benchmark generation Virtutech Simics – Test vector generation Design-level Methodology

17. Gradual Slack Distribution Slack optimization achieves gradual slack distribution.

18. Processor Module Optimization Slack optimized design has lowest power for all error rates.

19. Processor Error Rate and Power Designs with comparable error rates have much higher power/area overheads.

20. Reliability/Power Tradeoff Slack-optimized design enjoys continued power reduction as error rate increases.

21. Enhancing Razor-based Design Slack optimization extends range of voltage scaling and reduces Razor recovery cost.

22. Summary and Conclusion Showed limitations of traditional processors w.r.t. voltage scaling Traditional designs break down Presented design technique that enables voltage/reliability tradeoffs Optimize frequently exercised critical paths De-optimize rarely-exercised paths Demonstrated significant power benefits of gradual slack design Reduced power 29% for 2% error rate, 27% on average

23. Bonus Slides

24. Slack Optimization Techniques Path Optimization and Power Reduction

25. Extended Voltage Scaling Focus on frequently exercised negative slack paths Reduce error rate while minimizing cell swaps (power overhead) PathTGOpt. Rank A-B-C-D0.221 A-B-D0.152 A-C-D0.053 Rank paths by error rate contribution.Upsize cells in paths to increase slack. SWAP

26. Power Reduction Downsize cells on rarely exercised paths Reduce leakage power while leaving error rate unaffected SWAP Toggle Rate ≈ 0 Check Path Slack

27. Error Rate Forecasting Error rate contribution of one FF Error rate of design

28. Significance of Processor Power Power is a first-order design constraint Voltage scaling can significantly reduce power Voltage Scaling: 50%  Power Reduction: 80%

29. DVFS Benefit and Cost How effective is voltage scaling when frequency is fixed?

30. Alternatives – Blueshift Goal: Optimize paths that cause errors to enable more frequency overscaling Techniques: PCT/OSB Uses iterative simulation loop – infeasible for large designs

31. Alternatives – Tightly Constrained SP&R Goal: Optimize all paths aggressively Technique: Traditional SP&R with aggressive target Some paths will not meet tight constraint, and slack distribution becomes more gradual

32. Insight Optimize frequently exercised paths at the expense of rarely exercised paths Optimizing frequently exercised paths enables deeper voltage scaling De-optimizing rarely exercised paths keeps power overhead low

33. Iterative Optimization Flow Scale VoltageOptimize Paths Iterate

34. A New Processor Design Goal Reshape the slack distribution so processor fails gracefully

35. Moore’s Law Power consumption of processor node doubles every 18 months.

36. Power Scaling With current design techniques, processor power soon on par with nuclear power plant

37. Outline Background and Motivation Insight Power Reduction Techniques Design Flow Results Summary