1. 16-bit 4-stage Pipelined Microprocessor EECS 427 Project Group: JARS (John, Abhishek, Ramashis, Syed)

2. Block Diagram CONTROLLER On-Chip Memory (RAM) DATAPATH On-Chip Memory (ROM) I/O

3. Write Back Data Jump Target Write Jump PC IR PC RegA RegB Register File MUX ALU SHIFTER Data Memory (RAM) Sign Extend MUX +1 Instr Mem (ROM) Datapath – 4 Stages Stage 1 (Instruction Fetch) Sends PC to Instruction Memory Gets the Instruction Increments PC to PC+1 Stage 2 (Instruction Decode and Register Fetch) Instruction is Decoded in controller Operands for current Instruction is fetched from Register file/Instruction In case of Bypass, value is forwarded from previous instruction Stage 3 (ALU, Shifter, Memory Access) Operands are properly chosen and fed into the ALU, Shifter and Memory units Tri-state MUX is used to select the correct result to be fed into the data-bus Provision for data- forwarding PSR calculations and Branch Prediction done Stage 4 (Register Write-back and PC Update) Writes back the result in Destination Register In case of Jump, it loads PC with the new value

4. Simulation Results:

5. Simulation Results (… Contd)

6. External Read/Write Store and Load instructions are slightly modified to incorporate I/O from outside. Output Instruction: Store r0, rn % rn – contains address of data memory from where data has to be sent. ‘r0’ tells controller that it is an external output. Input Instruction: Load raddr’, r1 % raddr’[9] = ‘1’ which tells controller to store external data to memory address raddr’[8:0]. (Note: 9 th bit is unused for normal load operation as we are using 512 RAM) Idle-waiting has been implemented to wait for data till it is available to the μP.

7. Data Out RAM I/O Selector Output Buffer Output ReadyDATA INDATA OUT Outside world Inside Chip

8. Data Input (Idle waiting) Instruction Memory PCPC Interrupt Controller IRIR Input Ready load_enable +1

9. Project Done! DRC & LVS checked layout of μP without on- chip memory. DRC checked layout of μP with memory. Memory mapped data I/O with idle-waiting implemented. DFT: All internal datapath registers are part of Scan chain which facilitates testing.

10. Thank You - JARS