1. 1 A Fast, Analytical Estimator for the SEU-induced Pulse Width in Combinational Designs By: Rajesh Garg Charu Nagpal Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX

2. 2 Outline Introduction Introduction Previous Work Previous Work Objective Objective Approach Approach Classification of Radiation Particle Strikes Classification of Radiation Particle Strikes Our Model Our Model Experimental Results Experimental Results Conclusions Conclusions

3. 3 Introduction Modern VLSI Designs Modern VLSI Designs Vulnerable to noise effects- crosstalk, SEU, etc Vulnerable to noise effects- crosstalk, SEU, etc Single Event Upsets (SEUs) or Soft Errors Single Event Upsets (SEUs) or Soft Errors Troublesome for both memories and combinational logic Troublesome for both memories and combinational logic Becoming increasingly problematic even for terrestrial designs Becoming increasingly problematic even for terrestrial designs Applications demand reliable systems Applications demand reliable systems Need to efficiently design radiation tolerant circuits Need to efficiently design radiation tolerant circuits Analyze circuits early in design flow Analyze circuits early in design flow Hence need SEU robustness metric Hence need SEU robustness metric Harden the circuits using these metrics Harden the circuits using these metrics Approach depends on level of protection required Approach depends on level of protection required Need to satisfy delay, area and power constraints Need to satisfy delay, area and power constraints

4. 4 SEU Robustness Metrics SPICE based simulation of SEU events SPICE based simulation of SEU events Most accurate metric possible Most accurate metric possible Computationally expensive Computationally expensive Too many scenarios required to be simulated Too many scenarios required to be simulated Amount of charge dumped Amount of charge dumped State of circuit inputs State of circuit inputs Need to simulate all nodes in a circuit Need to simulate all nodes in a circuit Hence we need an efficient and accurate SEU robustness metric Hence we need an efficient and accurate SEU robustness metric This is the focus of this talk This is the focus of this talk

5. 5 SEU Robustness Metrics Accurate and efficient models for SEU events Accurate and efficient models for SEU events Can be used to harden a circuit Can be used to harden a circuit Requires solving of non-linear differential equations. Requires solving of non-linear differential equations. Our metric is based on the pulse width of voltage glitch due to a radiation strike Our metric is based on the pulse width of voltage glitch due to a radiation strike Good measure of SEU robustness Good measure of SEU robustness Based on the pulse width, we can upsize susceptible gates Based on the pulse width, we can upsize susceptible gates Easily incorporated in design flow Easily incorporated in design flow

6. 6 Radiation Particle Strike Effects of radiation particle strike Effects of radiation particle strike Neutron, proton and heavy cosmic ions Neutron, proton and heavy cosmic ions Ions strike diffusion regions Ions strike diffusion regions Deposit charge Deposit charge Results in a voltage spike Results in a voltage spike Radiation particle strike is modeled by a current pulse as Radiation particle strike is modeled by a current pulse as where: Q is the amount of charge deposited where: Q is the amount of charge deposited   is the collection time constant   is the ion track establishment constant   is the ion track establishment constant

7. 7 Previous Work Device-level simulation: Dodd et. al 1994, etc Device-level simulation: Dodd et. al 1994, etc Accurate but very time consuming Accurate but very time consuming Not practical for circuit hardening Not practical for circuit hardening Logic-level simulation: Cha et. al 1996 Logic-level simulation: Cha et. al 1996 Abstract transient faults by logic-level models Abstract transient faults by logic-level models Gate-level timing simulators are used Gate-level timing simulators are used Highly inaccurate as a robustness metric for hardening purposes Highly inaccurate as a robustness metric for hardening purposes Circuit-level simulation: Circuit-level simulation: Intermediate between device and logic level simulation Intermediate between device and logic level simulation

8. 8 Previous Work Shih et. al 1992 solve transistor non-linear differential equation using infinite power series Shih et. al 1992 solve transistor non-linear differential equation using infinite power series Computationally expensive Computationally expensive Dahlgren et. al 1995 presented switch level simulator Dahlgren et. al 1995 presented switch level simulator Electrical simulations are performed to obtain the pulse width of a voltage glitch, using the R and C values of a gate Electrical simulations are performed to obtain the pulse width of a voltage glitch, using the R and C values of a gate Pulse width for other R and C values are obtained using linear relationship between the obtained pulse width and the new R and C values Pulse width for other R and C values are obtained using linear relationship between the obtained pulse width and the new R and C values Cannot be used for different values of Q Cannot be used for different values of Q Mohanram 2005 reports a closed form model for SEU induced transient simulation for combinational circuits Mohanram 2005 reports a closed form model for SEU induced transient simulation for combinational circuits Linear RC gate model is used Linear RC gate model is used Ignores the contribution of   in i seu (t) – we find that this results in 10% error Ignores the contribution of   in i seu (t) – we find that this results in 10% error Results in lower accuracy Results in lower accuracy

9. 9 Objective Develop an analytical model for SEU induced transients in combinational circuits Develop an analytical model for SEU induced transients in combinational circuits Closed form analytical expression for the pulse width of voltage glitch Closed form analytical expression for the pulse width of voltage glitch Accurate and efficient Accurate and efficient Applicable to Applicable to Any logic gate Any logic gate Different gate sizes Different gate sizes Different gate loading Different gate loading Incorporates the contribution of   time constant Incorporates the contribution of   time constant Can be easily integrated in a design flow Can be easily integrated in a design flow

10. 10 Our Approach Radiation particle strike at the output of INV1 Radiation particle strike at the output of INV1 Implemented using 65nm PTM with VDD=1V Implemented using 65nm PTM with VDD=1V Radiation strike: Q =150fC,   =150ps &   =50ps Radiation strike: Q =150fC,   =150ps &   =50ps Models Radiation Particle Strike M1 in Linear M2 in Cutoff M1 in Saturation M2 in Cutoff M1 in Saturation M2 in Saturation M1 and M2 operate in different regions during radiation-induced transients Our approach estimates the pulse width of the transient by modeling these regions INV1 cannot be modeled accurately by a linear RC model (as was done in several previous approaches) M1 in Saturation M2 in Saturation M2’s Drain-Bulk diode is ON

11. 11 Classification of Radiation Strike INV1 can operate in 4 different cases depending upon voltage glitch magnitude V GM (=V a ) INV1 can operate in 4 different cases depending upon voltage glitch magnitude V GM (=V a ) Case 1: V GM ≥ VDD + 0.6V Case 1: V GM ≥ VDD + 0.6V Case 2: VDD+|V TP | ≤ V GM < VDD + 0.6V Case 2: VDD+|V TP | ≤ V GM < VDD + 0.6V Case 3: 0.5*VDD ≤V GM <VDD+|V TP | Case 3: 0.5*VDD ≤V GM <VDD+|V TP | Case 4: V GM < 0.5*VDD Case 4: V GM < 0.5*VDD Different analytical models are applicable to different cases to compute pulse width of the voltage glitch

12. 12 Model Overview Given a gate G, its input state, the gates in the fanout of G and Q,   and   Determine the value of V GM & case of operation If Case==4 Pulse Width is 0 YesNo Compute t 1 If Case==1 use its model to compute t 2 If Case==2 use its model to compute t 2 If Case==3 use its model to compute t 2 Compute Pulse Width as t 2 -t 1 Cell library data I DS (V DS ) forV GS =1 and 0, C G and C D

13. 13 Voltage Glitch Magnitude (V GM ) I DS of NMOS transistor with gate terminal at VDD I DS of NMOS transistor with gate terminal at VDD Differential equation for radiation induced voltage transient at output of INV1 Differential equation for radiation induced voltage transient at output of INV1 (1) (1) t Va(t)Va(t) Green  Known Red  Unknown Integrate Equation 1 from (0, 0) to (V dsat, T sat ) with T sat V dsat Solve for T sat Again integrate Equation 1 with initial condition (V dsat, T sat ) and with T V GM V GM Obtain T V GM by differentiating V a (t) and solving dV a (t)/dt = 0 Now V GM = V a (T V GM ) * Details can be found in the paper

14. 14 Voltage Glitch Magnitude (V GM ) V GM = V a (T V GM ) where V GM = V a (T V GM ) where X’, Y’ and Z’ are constants defined in the paper X’, Y’ and Z’ are constants defined in the paper is the time when i seu (t) is at its maximum value is the time when i seu (t) is at its maximum value Diff. eq. for radiation induced voltage transient at output of INV1 Diff. eq. for radiation induced voltage transient at output of INV1 Does not include the drain to source current of M2 (PMOS) Does not include the drain to source current of M2 (PMOS) Accurate for Case 3 and 4 Accurate for Case 3 and 4 In some cases, Case 2 V GM value can be diagnosed as Case 1- Pessimistic In some cases, Case 2 V GM value can be diagnosed as Case 1- Pessimistic

15. 15 Next Steps Once we know V GM, we know which case is applicable (among cases 1, 2, and 3). Once we know V GM, we know which case is applicable (among cases 1, 2, and 3). The magnitude of the SET induced glitch is t 2 – t 1 The magnitude of the SET induced glitch is t 2 – t 1 Next, we find an expression for t 1 (common for all 3 cases) Next, we find an expression for t 1 (common for all 3 cases) Then we will find expressions for t 2 (separately for each of the 3 cases) Then we will find expressions for t 2 (separately for each of the 3 cases) Note that case 4 is not of interest since the glitch magnitude is less than VDD/2 in case 4. Note that case 4 is not of interest since the glitch magnitude is less than VDD/2 in case 4. Lets do this over the next few slides… Lets do this over the next few slides…

16. 16 Expression for t 1 If V GM > 0.5*VDD then there is a glitch If V GM > 0.5*VDD then there is a glitch t Va(t)Va(t) Green  Known Red  Unknown T sat V dsat T V GM V GM To obtain t 1, substitute V a (t 1 ) = 0.5*VDD and solve for t 1 using initial guess t1t1 0.5*VDD

17. 17 Expression for t 2 : Case 1 For Case 1, V GM ≥ VDD+0.6V For Case 1, V GM ≥ VDD+0.6V V a (t 3 ) = VDD +|V TP | V a (t 3 ) = VDD +|V TP | I DS of PMOS M2 is zero I DS of PMOS M2 is zero i seu (t 3 ) = I DS of M1 i seu (t 3 ) = I DS of M1 Also ignore   Also ignore   This gives us t 3 below This gives us t 3 below Use, V a (t) = VDD +|V TP | Use, V a (t) = VDD +|V TP | at t = t 3 as initial condition for integration. for integration. VDD+|V TP | t3t3

18. 18 Expression for t 2 : Case 1 Approximate i seu (t) by a straight line Approximate i seu (t) by a straight line t Va(t)Va(t) Green  Known Red  Unknown t3t3 V DD +|V TP | V GM t1t1 0.5*VDD t2t2 i seu (t) Va(t)Va(t) t*t* Integrate Equation 1 with initial condition (VDD+|V TP |, t 3 ) Substitute V a (t) = 0.5*VDD for t = t 2 and solve for t 2 by performing a quadratic expansion around initial guess P, Q, R and t* are constants defined in the paper P, Q, R and t* are constants defined in the paper Details of derivation of t 2 can be found in the paper

19. 19 Expression for t 2 : Case 2 For Case 2: VDD+|V TP |≤V GM <VDD+0.6V For Case 2: VDD+|V TP |≤V GM <VDD+0.6V Again use initial condition, V a (t)=VDD+|V TP | at t = t 3 Again use initial condition, V a (t)=VDD+|V TP | at t = t 3 t Va(t)Va(t) Green  Known Red  Unknown t3t3 V DD +|V TP | T V GM V GM t1t1 0.5*VDD t2t2 Integrate Equation 1 with initial condition (VDD+|V TP |, t 3 ) To obtain t 2, substitute V a (t 2 )=0.5*VDD and solve for t 2 by using initial guess

20. 20 Expression for t 2 : Case 3 For Case 3: For Case 3: 0.5*VDD≤V GM <VDD+|V TP | 0.5*VDD≤V GM <VDD+|V TP | t Va(t)Va(t) Green  Known Red  Unknown T sat V dsat T V GM V GM To obtain t 2, substitute V a (t 2 )=0.5*VDD and solve for t 2 by using initial guess t1t1 0.5*VDD t2t2

21. 21 Experimental Results Implemented our model in Perl Implemented our model in Perl Library of INV, NAND and NOR gates Library of INV, NAND and NOR gates Using 65nm PTM model card with VDD=1V Using 65nm PTM model card with VDD=1V Characterized each gate for I DS, C G and C D Characterized each gate for I DS, C G and C D Applied our model to INV and NAND2 Applied our model to INV and NAND2 For different values of Q,   and   For different values of Q,   and   Different gate sizes and loads Different gate sizes and loads Our model is 1000X faster compared to SPICE Our model is 1000X faster compared to SPICE

22. 22 Experimental Results Radiation particle strike at the output INV1 with Q=150fC,   =150ps and   = 50ps Radiation particle strike at the output INV1 with Q=150fC,   =150ps and   = 50ps INV1 with input 1INV1 with input 0 LoadSizePW S (ps)PW M (ps)% ErrorPW S (ps)PW M (ps)% Error 11533 05175220.97 124144150.244044101.49 142922961.372852984.56 162132234.6920823111.06 181421462.821401410.71 315525530.18535533-0.37 324324340.46420 0 343083152.273013061.66 362272395.29221 0 381471523.41471480.68 AVG2.072.15

23. 23 Experimental Results NAND2 gate with Q=150fC,   =150ps and   = 50ps NAND2 gate with Q=150fC,   =150ps and   = 50ps Average pulse width estimation error compared to SPICE Average pulse width estimation error compared to SPICE INPUT 11INPUT 00INPUT 01INPUT 10 LoadSize% Error 110-0.74-0.19-0.56 120.781.050.24-0.24 143.050.712.411.67 1610.34-7.55-0.45 310.580.24-0.55-0.36 321.252.39-0.240 344.010.691.641.27 363.8-00 AVG 2.970.971.60.57

24. 24 Conclusion A SEU robustness metric is required to design radiation tolerant circuits efficiently A SEU robustness metric is required to design radiation tolerant circuits efficiently We presented an analytical model to compute this metric (which is the pulse width of the SEU induced glitch) We presented an analytical model to compute this metric (which is the pulse width of the SEU induced glitch) Pulse width of the glitch is a good measure of SEU robustness Pulse width of the glitch is a good measure of SEU robustness Our model is accurate and efficient Our model is accurate and efficient Pulse width estimation error is 3% compared to SPICE Pulse width estimation error is 3% compared to SPICE Our method is 1000X faster than SPICE Our method is 1000X faster than SPICE Our model gains accuracy Our model gains accuracy By using the transistor current model (and avoiding a linear RC model for the gate) By using the transistor current model (and avoiding a linear RC model for the gate) By including the contribution of   By including the contribution of   Our model can be easily incorporated in a design flow to test robustness. Based on the results, hardening can be performed. Our model can be easily incorporated in a design flow to test robustness. Based on the results, hardening can be performed.

25. 25 Thank You Thank You

26. 26 BACKUP SLIDES BACKUP SLIDES

27. 27 Voltage Glitch Magnitude (V GM ) I DS of NMOS transistor with gate terminal at VDD I DS of NMOS transistor with gate terminal at VDD For 65nm PTM model card V dsat < 0.5*VDD For 65nm PTM model card V dsat < 0.5*VDD Integrate Eq. 1 from V a (t)=0 at t=0 to V a (t)=V dsat at t=T sat using I DS = Va/R DS Integrate Eq. 1 from V a (t)=0 at t=0 to V a (t)=V dsat at t=T sat using I DS = Va/R DS Solve for T sat by linearly expanding around initial guess T a sat, we get Solve for T sat by linearly expanding around initial guess T a sat, we get

28. 28 Voltage Glitch Magnitude (V GM ) To calculate T a sat, approximate the rising part of i seu (t) by a line To calculate T a sat, approximate the rising part of i seu (t) by a line Substitute i seu (t) in Eq. 1 by a line between origin and I max seu Substitute i seu (t) in Eq. 1 by a line between origin and I max seu Integrate Eq. 1 from V a (t)=0 at t=0 to V a (t)=V dsat at t=T a sat Integrate Eq. 1 from V a (t)=0 at t=0 to V a (t)=V dsat at t=T a sat Solve for T a sat by quadratic expansion around origin Solve for T a sat by quadratic expansion around origin Now, integrate Eq. 1 with initial condition V a (t)=V dsat at t=T sat Now, integrate Eq. 1 with initial condition V a (t)=V dsat at t=T sat Use I DS = K 3 + K 4.V DS for this integration Use I DS = K 3 + K 4.V DS for this integration(2)

29. 29 Voltage Glitch Magnitude (V GM ) Differentiate V a (t) (Eq. 2) and solve dV a (t)/dt =0 for T V GM Differentiate V a (t) (Eq. 2) and solve dV a (t)/dt =0 for T V GM Linearly expand around T max seu Linearly expand around T max seu Now, V GM = V a (T V GM ) Now, V GM = V a (T V GM ) If V GM > VDD + 0.6V then set V GM = VDD + 0.6V If V GM > VDD + 0.6V then set V GM = VDD + 0.6V Diode is not modeled in Eq. 2 Diode is not modeled in Eq. 2

30. 30 Expression for t 1 If V GM > 0.5*VDD then there is a glitch If V GM > 0.5*VDD then there is a glitch Substitute t = t 1 and V a (t 1 ) = 0.5*VDD in Eq. 2 Substitute t = t 1 and V a (t 1 ) = 0.5*VDD in Eq. 2 Expand linearly around t a 1 = T sat VDD/(2V dsat ) Expand linearly around t a 1 = T sat VDD/(2V dsat ) (3) (3) Eq. 3 is used to compute t 1 for Cases 1, 2 and 3 Eq. 3 is used to compute t 1 for Cases 1, 2 and 3

31. 31 Expression for t 2 : Case 1 For Case 1, V GM ≥ VDD+0.6V For Case 1, V GM ≥ VDD+0.6V V a (t 3 ) = VDD-|V TP | V a (t 3 ) = VDD-|V TP | I DS of PMOS M2 is zero I DS of PMOS M2 is zero i seu (t 3 ) = I DS of M1 i seu (t 3 ) = I DS of M1 Use, V a (t) = VDD-|V TP | Use, V a (t) = VDD-|V TP | at t = t 3 as initial condition To calculate t 3, ignore   in i seu (t) To calculate t 3, ignore   in i seu (t)   is 3-4 times larger than     is 3-4 times larger than   e -t/   around t 3 will be close to 0 e -t/   around t 3 will be close to 0 VDD-|V TP | t3t3

32. 32 Expression for t 2 : Case 1 Model i seu (t) by a straight line for t >t 3 between (I DS avg,t 3 ) and (0, t*) Model i seu (t) by a straight line for t >t 3 between (I DS avg,t 3 ) and (0, t*) TBD what is ids avg TBD what is ids avg Obtain t* by equating charge deposited by i seu (t) and the above straight line model for t >t 3 Obtain t* by equating charge deposited by i seu (t) and the above straight line model for t >t 3 Integrate INV1 output node diff. equation (Eq. 1) Integrate INV1 output node diff. equation (Eq. 1) Initial condition: V a (t) = VDD-|V TP | for t = t 3 Initial condition: V a (t) = VDD-|V TP | for t = t 3 Substitute V a (t) = 0.5*VDD for t = t 2 and solve for t 2 Substitute V a (t) = 0.5*VDD for t = t 2 and solve for t 2 t 2 a1 is the initial guess for t 2 t 2 a1 is the initial guess for t 2 Integrate Eq. 1 with I DS Va = I DS VDD+|VTP| and line mode for i seu (t) Integrate Eq. 1 with I DS Va = I DS VDD+|VTP| and line mode for i seu (t) Substitute V a (t) = 0.5*VDD for t = t 2 a1 and solve for t 2 a1 Substitute V a (t) = 0.5*VDD for t = t 2 a1 and solve for t 2 a1 Closed form exp. of t 2 a1 is Closed form exp. of t 2 a1 is

33. 33 Expression for t 2 : Case 2 In this case also, V a (t 3 ) = VDD-|V TP | In this case also, V a (t 3 ) = VDD-|V TP | Integrate INV1 output node diff. equation (Eq. 1) Integrate INV1 output node diff. equation (Eq. 1) Initial condition: V a (t) = VDD-|V TP | for t = t 3 Initial condition: V a (t) = VDD-|V TP | for t = t 3 Use original expressions for i seu (t) and I DS Va Use original expressions for i seu (t) and I DS Va Substitute V a (t) = 0.5*VDD for t = t 2 Substitute V a (t) = 0.5*VDD for t = t 2 Expand around initial guess t 2 a2 for t 2 and solve for t 2 Expand around initial guess t 2 a2 for t 2 and solve for t 2 Calculate t 2 a2 by solving equation i seu (t 2 a2 )= I DS VDD/2 Calculate t 2 a2 by solving equation i seu (t 2 a2 )= I DS VDD/2 t 2 a2 > T seu max (Time when i seu (t) reaches its maximum value) t 2 a2 > T seu max (Time when i seu (t) reaches its maximum value) Ignore e -t/   term in i seu (t) Ignore e -t/   term in i seu (t)

34. 34 Expression for t 2 : Case 3 In this case, only M1 conducts In this case, only M1 conducts Substitute V a (t) = 0.5*VDD for t = t 2 in Eq. 2 Substitute V a (t) = 0.5*VDD for t = t 2 in Eq. 2 V a (t) equation as shown before V a (t) equation as shown before Solve for t 2 after e xpanding around initial guess t 2 a2 for t 2 Solve for t 2 after e xpanding around initial guess t 2 a2 for t 2 where where Now we can calculate the pulse width as t 2 - t 1 Now we can calculate the pulse width as t 2 - t 1