1. Design, Verification, and Test of True Single-Phase Adiabatic Multiplier Suhwan Kim IBM Research Division T. J. Watson Research Center, Yorktown Heights Conrad H. Ziesler and Marios C. Papaefthymiou Electrical Engineering and Computer Science University of Michigan, Ann Arbor

2. Adiabatic Charging of an RC Tree Charge and discharge load capacitance slowly to maintain small voltage drop across MOS switches and recycle energy stored in load capacitance.

3. Adiabatic Logic Families Various adiabatic logic families,including 2N-2P, Pass-Transistor Aiabdatic Logic (PAL), and Clocked CMOS Adiabatic Logic (CAL), have been proposed. True Single-Phase Energy-Recovery Logic (TSEL) is the first-ever true single-phase adiabatic logic family. [Suhwan Kim and Marios.C. Papaefthymiou, ISLPED’98]. Source-Coupled Adiabatic Logic (SCAL) is an enhancement of TSEL with improved scalability and energy efficiency across a broad range of operating frequencies. [Suhwan Kim and Marios. C. Papaefthymiou, ISLPED’99].

4. SCAL-D: Source-Coupled Adiabatic Logic with Diode-Connected Transistors Basic characteristics of SCAL-D are the same as with SCAL/TSEL. single-phase AC power-clock operation simple AC power-clock generator simple to cascade Individually tunable current source attached to each gate. broad range of operating frequencies with minimum-size transistors Diode-connected transistors used to improve performance.

5. PMOS Logic Structure in SCAL-D Each logic gate comprises a pair of cross-coupled transistors, diode- connected transistors, current control switches, a pull-up evaluation tree, and a tunable current source.

6. Operation of PMOS Logic in SCAL-D

7. NMOS Logic Structure in SCAL-D Basic structure is the same as in PMOS SCAL-D, with NMOS devices replaced by PMOS devices

8. Cascading of SCAL-D Logic Energy consumption is minimized by individually setting the W/L ratio of each current source and globally setting the biasing voltages equal to the minimum possible value. This value depends on the gate’s output load and speed requirement.

9. Voltages of Output Nodes in Cascaded SCAL-D

10. 8-bit Multiplier and BIST Logic in SCAL-D

11. Schematic Diagram of Full-Adder Multiplier Cell in SCAL-D

12. Full-Custom Layout of Full-Adder Multiplier Cell in SCAL-D 1-bit full adder buffer and

13. Full-Custom Layout of 8-bit Multiplier and BIST Logic in SCAL-D 8-bit multiplier BILBO 2 BILBO 1 self-test controller

14. Transistor Count and Area of 8-bit Multiplier and BIST Logic in SCAL-D Transistor Count 11,854 Area 0.710mm^2 Built-in self-test logic8-bit multiplier

15. Evaluation with Voltage Scaling In HSPICE simulations, our SCAL-D 8-bit multiplier and BIST logic outperformed corresponding static CMOS designs that were operating with supply voltages scaled for minimum energy dissipation.

16. Design Verification of 8-bit Multiplier and BIST Logic in SCAL-D The results of HSPICE simulation were compared directly against the corresponding results of Verilog-HDL simulation using CAD tools we developed. power-clock BILBO control signals s1,s2 output sequence ix of BILBO 1 output sequence ox of BILBO 2

17. Floor-plan of Test-Chip Floor-plan of Test-Chip Two identical multipliers with associated BIST logic, an internal power-clock generator, adiabatic-to-digital converters, and pads were included.

18. Die Photograph of Test-Chip Fully custom design 0.5um n-well CMOS process DIP40 package 4.83mm^2 130 MHz operation with 3.0V

19. Experimental Setup digitaloscilloscope(TDS754D) signal generator (HP8647A) test-board DC power supply digital multi-meters

20. Test-Board test-chip switches for input signals variable resistors to control PMOS and NMOS biasing voltages connector for external power-clock

21. Functional Test in Self-Test Mode: 50MHz/3.0V power-clock BILBO control signals s2 output sequence ix of BILBO 1 output sequence ox of BILBO 2

22. power-clock BILBO control signals s2 output sequence ix of BILBO 1 output sequence ox of BILBO 2 Functional Test in Self-Test Mode: 130MHz/3.0V

23. Energy Measurement Procedures chippower supply

24. Measured Energy Consumption of 8-bit Multiplier and BIST Logic in SCAL-D Energy consumption in the 8-bit multiplier and BIST logic, implemented entirely using SCAL-D, for various PMOS and NMOS biasing voltages at the operating frequency range of 40-130 MHz.

25. Relative Difference of Energy Consumption Between TDS754D and HSPICE Measured energy consumption of SCAL-D circuits correlates well with HSPICE simulation results for the same operating frequencies, amplitude of AC power-clock, DC supply voltage, and PMOS and NMOS biasing voltages.

26. Measured Waveforms of Test-Chip Operated in BIST Mode - 130MHz/3.0V power-clock BILBO control signals s2 output sequence ix of BILBO 1 output sequence ox of BILBO 2

27. Summary True single-phase source-coupled adiabatic logic family Lower energy dissipation than static CMOS across broad range of operating frequencies. To demonstrate practicality of our single-phase adiabatic logic, we designed an 8-bit adiabatic multiplier in 0.5um standard CMOS process. The 8-bit adiabatic multiplier and BIST logic was verified, fabricated, tested, and measured up to 130 MHz.