1. 1 Exceptions, Interrupts, and the OS STOP!! Do this!!!

2. 2 Interrupts Have device tell OS/CPU it is readyHave device tell OS/CPU it is ready Requires hardware to support.Requires hardware to support. OS/CPU can then interrupt what it is doing to:OS/CPU can then interrupt what it is doing to: Determine what device wants serviceDetermine what device wants service Determine what service it wantsDetermine what service it wants Perform or start the servicePerform or start the service Go back to what OS/CPU was doingGo back to what OS/CPU was doing “External condition related to IO devices”

3. 3 Interrupts Examples of Interrupts Disk drive at sector/track position (old days) Disk drive at sector/track position (old days) Mouse moved Mouse moved Keyboard key pressed Keyboard key pressed Printer out of paper Printer out of paper Video card wants memory access Video card wants memory access Modem sending or receiving Modem sending or receiving USB scanner has data USB scanner has data

4. 4 Interrupts Interrupt Properties They arrive asynchronouslyThey arrive asynchronously Can’t communicate with a running program (no args or return values)Can’t communicate with a running program (no args or return values) They are associated with various prioritiesThey are associated with various priorities You want to handle them soon (interrupt latency)You want to handle them soon (interrupt latency) (usually) want to resume program(usually) want to resume program

5. 5 Trap “Internal conditions related to instruction stream” Trap Examples: “TRAP” instruction “TRAP” instruction Illegal instruction Illegal instruction Arithmetic overflow Arithmetic overflow Divide by zero Divide by zero “LD” from illegal/protected memory address “LD” from illegal/protected memory address

6. 6 They arrive synchronously They arrive synchronously Get trap in same place if you re-run program Get trap in same place if you re-run program They are associated with various priorities They are associated with various priorities Must handle immediately Must handle immediately Want to resume program (usually) Want to resume program (usually) Trap Properties

7. 7 Exceptions “Mechanism used to handle both interrupts and traps” HW handles initial reactionHW handles initial reaction Then invokes SW called an “Exception Handler” to take care of the interrupt/trapThen invokes SW called an “Exception Handler” to take care of the interrupt/trap

8. 8 HC11 Exceptions HC11 is real hardware and thus has mechanisms to deal with both Traps and Interrupts.HC11 is real hardware and thus has mechanisms to deal with both Traps and Interrupts. We will deal with interrupts only.We will deal with interrupts only. HC11 does things very similar to the LC-3.HC11 does things very similar to the LC-3. Uses an “Interrupt Vector” table to find address of interrupt and goes straight to specific Interrupt Service Routine (ISR).Uses an “Interrupt Vector” table to find address of interrupt and goes straight to specific Interrupt Service Routine (ISR).

9. 9 HC11 Micro Kit Jump Table // 1unavailable to userSCI ISR_JUMP2EQU0x7BC5//SPI ISR_JUMP3EQU0x7BC8// Pulse Accumulator Input ISR_JUMP4EQU0x7BCB// Pulse Accumulator Overflow // 5unavailable to userTimer Overflow // 6unavailable to userOutput Compare 5 ISR_JUMP7EQU0x7BD4// Output Compare 4 ISR_JUMP8EQU0x7BD7// Output Compare 3 ISR_JUMP9EQU0x7BDA// Output Compare 2 ISR_JUMP10EQU0x7BDE// Output Compare 1 ISR_JUMP11EQU0x7BE3// Input Capture 3 ISR_JUMP12EQU0x7BE6// Input Capture 2 ISR_JUMP13EQU0x7BE9// Input Capture 1 // 14unavailable to userReal Time Interrupt ISR_JUMP15EQU0x7BEC// IRQ – Button on Kit // 16unavailable to userXIRQ // 17unavailable to userSWI // 18unavailable to userIllegal Opcode ISR_JUMP19EQU0x7BF8// Cop fail ISR_JUMP20EQU0x7BFB// Cop clock fail // 21unavailable to userReset (found at 0x8040) See Motorola documentation for discussion of unavailable vectors. HC11 Exceptions

10. 10 Configuring interrupts for the HC11 is pretty easy. What you need to do is: 1) Make an ISR, it is just like a procedure but returns with RTI. 2) Put the address of the ISR into the Jump Table. Example: // initializes the ISR jump vectors to our interrupt service routines // jump vectors are defined in v2_18g3.asm ldx #BUTTON_isr stx ISR_JUMP15 BUTTON_isr: // Put your code in here. Do not do any I/O in an ISR … // Use this to return from an interrupt rti HC11 Exceptions

11. 11 1.Wait for current instruction to complete 2.Disable further interrupts 3.Save all CPU registers and return address on stack 4.Access “interrupt vector table” according to source 5.Jump to where the interrupt routine is specified in table 6.Use RTI to return HC11 Hardware Mechanism

12. 12 LC-3 Exceptions LC-3 only has the concept of IO related exceptions, interrupts.LC-3 only has the concept of IO related exceptions, interrupts. Does not have any mechanisms to deal with illegal instructions, or arithmetic overflow.Does not have any mechanisms to deal with illegal instructions, or arithmetic overflow. Remember the LC-3 is just a learning aid, not real hardware.Remember the LC-3 is just a learning aid, not real hardware.

13. 13 LC-3 Interrupt-Driven I/O External device can: (1)Force currently executing program to stop; (2)Have the processor satisfy the device’s needs; and (3)Resume the stopped program as if nothing happened. Why do interrupts? –Polling consumes a lot of cycles, especially for rare events – these cycles can be used for more computation. –Example: Process previous input while collecting current input. (See Example 8.1 in text.)

14. 14 LC-3 Interrupt-Driven I/O To implement an interrupt mechanism, we need: –A way for the I/O device to signal the CPU that an interesting event has occurred. –A way for the CPU to test whether the interrupt signal is set and whether its priority is higher than the current program. Generating Signal –Software sets "interrupt enable" bit in device register. –When ready bit is set and IE bit is set, interrupt is signaled. ready bit KBSR 1514 0 13 interrupt enable bit interrupt signal to processor

15. 15 Priority Every instruction executes at a stated level of urgency. LC-3: 8 priority levels (PL0-PL7) –Example: Payroll program runs at PL0. Nuclear power correction program runs at PL7. –It’s OK for PL6 device to interrupt PL0 program, but not the other way around. Priority encoder selects highest-priority device, compares to current processor priority level, and generates interrupt signal if appropriate. LC-3 Interrupt-Driven I/O

16. 16 Testing for Interrupt Signal CPU looks at signal between STORE and FETCH phases.CPU looks at signal between STORE and FETCH phases. If not set, continues with next instruction.If not set, continues with next instruction. If set, transfers control to interrupt service routine.If set, transfers control to interrupt service routine. EA OP EX S S F F D D interrupt signal? Transfer to ISR Transfer to ISR NO YES LC-3 Interrupt-Driven I/O

17. 17 Full Implementation of LC-3 Memory- Mapped I/O Because of interrupt enable bits, status registers (KBSR/DSR) must now be written, as well as read.

18. 18 LC-3 Interrupts: 1.External device signals need to be serviced. 2.Processor saves state and starts service routine. 3.When finished, processor restores state and resumes program. An interrupt is an unscripted subroutine call, triggered by an external event. LC-3 Handling of interrupts

19. 19 Processor State What state is needed to completely capture the state of a running process? Processor Status Register –Privilege [15], Priority Level [10:8], Condition Codes [2:0] Program Counter –Pointer to next instruction to be executed.Registers –All temporary state of the process that’s not stored in memory. LC-3 Handling of interrupts

20. 20 Where to Save Processor State? Can’t use registers. –Programmer doesn’t know when interrupt might occur, so she can’t prepare by saving critical registers. –When resuming, need to restore state exactly as it was. Memory allocated by service routine? –Must save state before invoking routine, so we wouldn’t know where. –Also, interrupts may be nested – that is, an interrupt service routine might also get interrupted! Use a stack! –Location of stack “hard-wired”. –Push state to save, pop to restore. LC-3 Handling of interrupts

21. 21 Operating Systems The “program” that runs the user programs and deals with exceptions.The “program” that runs the user programs and deals with exceptions. How does the operating system deal with such things as simultaneous exceptions?How does the operating system deal with such things as simultaneous exceptions? What happens on machines that have many users “on” at once?What happens on machines that have many users “on” at once?

22. 22 Multiple Exceptions Problem: How about multiple simultaneous exceptions? Solution: Have priorities in HW / SW Handle highest-priority exception first Handle highest-priority exception first Equal priority exceptions handled arbitrarily Equal priority exceptions handled arbitrarily Give higher priority Give higher priority more serious (e.g., power failing) more serious (e.g., power failing) can’t wait long (e.g., rotating disk) can’t wait long (e.g., rotating disk) Operating Systems

23. 23 Operating Systems: Multiple Exceptions How about exceptions during exception handling? Make it wait until done with first exception Make it wait until done with first exception May be a bad idea for higher priority exceptionMay be a bad idea for higher priority exception Make exception handler re-entrant Make exception handler re-entrant Make able to handle multiple active callsMake able to handle multiple active calls Allow higher-priority exceptions to bypass lower- priority exception currently being servicedAllow higher-priority exceptions to bypass lower- priority exception currently being serviced

24. 24 Implementing a Re-entrant exception handler Initial exception disables all interruptsInitial exception disables all interrupts Exception handler (EH) determines exception’s priorityException handler (EH) determines exception’s priority EH saves any state that could be clobbered by higher priority interrupts (e.g. EPC)EH saves any state that could be clobbered by higher priority interrupts (e.g. EPC) EH re-enables higher-priority interruptsEH re-enables higher-priority interrupts Higher-priority interrupts may or may nor occurHigher-priority interrupts may or may nor occur This EH eventually finishesThis EH eventually finishes Operating Systems: Multiple Exceptions

25. 25 Multiprogramming An active program is called a “process” or “task” A process’ state is: program counter program counter registers registers memory locations being used memory locations being used Some OS memory Some OS memory The ability to run one or more programs “simultaneously” on one CPU. Operating Systems

26. 26 Operating Systems: Multiprogramming OS has one exception handler called the “kernel” OS has one exception handler called the “kernel” On an exception, CPU jumps into the kernel On an exception, CPU jumps into the kernel Kernel will eventually resume the user process Kernel will eventually resume the user process If the user process needs I/O (disk read) If the user process needs I/O (disk read) Kernel schedules it Kernel schedules it 20ms is ~ 2 million instructions 20ms is ~ 2 million instructions Start (or switch to) another task (multitasking) Start (or switch to) another task (multitasking) If user process does not need I/O If user process does not need I/O Kick it out (context switch) after some amount of time Kick it out (context switch) after some amount of time Every X clock cycles interrupt and switch again Every X clock cycles interrupt and switch again

27. 27 OS has several job queues - An entry is the complete state of a process Some queue examples: A queue of ready jobs with priority A queue of ready jobs with priority A queues for I/O device(s) A queues for I/O device(s) Jobs are moved to ready queue when I/O complete Jobs are moved to ready queue when I/O complete A queue of sleeping or halted jobs A queue of sleeping or halted jobs OS picks jobs from the ready queue as appropriate Operating Systems: Multiprogramming

28. 28 Generalized Exceptions 1.User program running 2.Exception is generated Internal/ExternalInternal/External Trap/InterruptTrap/Interrupt 3.Determine source of exception Requires a bus cycle for some peripheral bus architectures.Requires a bus cycle for some peripheral bus architectures. 4.Save return PC and any status registers modified by hardware LC-3: PC, PSR, registers R0-R7LC-3: PC, PSR, registers R0-R7 HC11: PC, index registers, accumulatorsHC11: PC, index registers, accumulators

29. 29 Generalized Exceptions 5.Jump to exception handler LC-3: Uses a jump tableLC-3: Uses a jump table HC11: Jump table starting at 0xFFD6HC11: Jump table starting at 0xFFD6 68000: Jump to location specified by interrupt device – vectored interrupts68000: Jump to location specified by interrupt device – vectored interrupts 6.Save state used by exception handler 7.Go to specific case Check exception typeCheck exception type Query deviceQuery device Check syscall registerCheck syscall register

30. 30 Generalized Exceptions 8.Process Exception Enable higher-priority interrupts if possibleEnable higher-priority interrupts if possible For interrupt, clear device’s interrupt flagFor interrupt, clear device’s interrupt flag Check device for multiple conditionsCheck device for multiple conditions 9.Restore state used by exception handler 10.Return from exception Restore modeRestore mode Restore hardware-saved stateRestore hardware-saved state Jump back to user programJump back to user program or exception handleror exception handler

31. 31 Exceptions Summary Exceptions (interrupts and traps) are a combination of hardware and software.Exceptions (interrupts and traps) are a combination of hardware and software. The hardware detects the exception and then calls software (OS or service routines) to handle it.The hardware detects the exception and then calls software (OS or service routines) to handle it. Much more efficient than polling but requires specialized hardware.Much more efficient than polling but requires specialized hardware.

32. 32 Questions?

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