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1 Computer System Overview Chapter 1 Review of basic hardware concepts.

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Presentation on theme: "1 Computer System Overview Chapter 1 Review of basic hardware concepts."— Presentation transcript:

1 1 Computer System Overview Chapter 1 Review of basic hardware concepts

2 Chapter 1 2 The OS and the Hardware n An Operating System makes the computing power available to users by controlling the hardware n Let us review the aspects of computer hardware which are important for the OS

3 Chapter 1 3 Basic Components n Processor (CPU) n Main Memory (RAM, primary memory) u holds data and code n I/O modules (I/O controllers, I/O channels, I/O processors...) u hardware (with registers called I/O ports) that moves data between CPU and peripherals like: F secondary memory devices (ex: hard disks) F keyboard, display... F communications equipment n System interconnection (buses, channels) u communication among processors, memory, and I/O modules

4 Chapter 1 4 Main Components PSW = Program Status Word PSW

5 Chapter 1 5 CPU Registers (fast memory on CPU) n Control & Status Registers u generally not available to user programs u some used by CPU to control its operation u some used by OS to control program execution n User-visible Registers u available to system (OS) and user programs u only visible when using machine and assembly languages u hold data, addresses, and some condition codes

6 Chapter 1 6 Examples of Control & Status Registers n Program Counter (PC) u Contains the address of the next instruction to be fetched n Instruction Register (IR) u Contains the instruction most recently fetched n Program Status Word (PSW) u A register or group of registers containing: F condition codes and status info bits F Interrupt enable/disable bit F Supervisor(OS)/user mode bit

7 Chapter 1 7 User-Visible Registers n Data Registers u dedicated to contain data information. Can have many functions, depending on the structure of the machine code and on programmer’s decisions (accumulator, etc.) n Address Registers u contain memory address of data and instructions u may contain a portion of an address that is used to calculate the complete address

8 Chapter 1 8 User-Visible Address Registers u Index/Offset F involves adding an index to a base value to get an address u Segment pointer F when address space is divided into segments, memory is referenced by a segment number and an offset u Stack pointer F points to top of stack F for subroutine entry/exit (Appendix 1B)

9 Chapter 1 9 User-Visible Registers n Condition Codes or Flags u Bits set by the processor hardware as a result of operations u Can be set by a program but not changed directly u Examples F sign flag F zero flag F overflow flag

10 Chapter 1 10 The Basic Instruction Cycle n The CPU fetches the next instruction (with operands) from memory. n Then the CPU executes the instruction n Program counter (PC) holds address of the instruction to be fetched next n Program counter is automatically incremented after each fetch

11 Chapter 1 11 In the simplest machine organization, CPU must wait for I/O completion n WRITE transfers control to the printer driver (I/O pgm) n I/O pgm prepares I/O module for printing (4) n CPU has to WAIT for I/O command to complete n I/O pgm finishes and reports status of operation è CPU wastes much time waiting

12 Chapter 1 12 Interrupts n Invented to allow overlap of input and processing times n CPU launches I/O, returns to processing and then gets interrupted when I/O completed n The I/O module sends an interrupt request on the control bus n Then CPU transfers control to an Interrupt Handler Routine (normally part of the OS)

13 Chapter 1 13 Instruction Cycle with Interrupts n If interrupts are enabled, CPU checks for interrupts after each instruction n If no interrupts, then fetch the next instruction for the current program n If an interrupt is pending, then suspend execution of the current program, and execute the interrupt handler (in the OS) n Note: disabling interrupts should be done only when really necessary, because it can cause loss of information.

14 Chapter 1 14 Interrupt Handling: similar to subroutine call but it is not controlled by user program User program must restart as if there was no interruption

15 Chapter 1 15 Interrupt Handler n Is a program that determines nature of the interrupt and performs whatever actions are needed n Upon interrupt, control is transferred to this program u This is done by transferring control to a memory location that is determined by the type of interruption: interrupt vector u Control must be transferred back to the interrupted program so that it can be resumed from the point of interruption n The point of interruption can be anywhere in the program (except where interrupt inhibited). n Thus: must save the state of the process (content of PC + PSW + registers +...)

16 Chapter 1 16 Simple Interrupt Processing Save Process Control Block Restore Process Control Block

17 Chapter 1 17 Interrupts improve CPU usage n I/O pgm prepares the I/O module and issues the I/O command (eg: to printer) n Control returns to user pgm n User code gets executed during I/O operation: no waiting n User pgm gets interrupted (x) when I/O operation is done n Control goes to interrupt handler to check status of I/O module and perform necessary processing n Execution of user code resumes

18 Chapter 1 18 Interrupts: terminology n Not normalized, but it is a good idea to distinguish between: u traps or exceptions: caused by the pgm as it executes F division by 0 F illegal access F system calls... u interruptions: caused by independent events: F end I/O F timers u faults: term used esp. in connection with paging and segmentation n But the hardware mechanisms are similar for all

19 Chapter 1 19 Multiple interrupts: sequential order n Disable interrupts during an interrupt n Interrupts remain pending until the processor enables interrupts n After interrupt handler routine completes, the processor checks for additional interrupts

20 Chapter 1 20 Multiple Interrupts: priorities n Higher priority interrupts cause lower-priority interrupts to wait n Causes a lower-priority interrupt handler to be interrupted n Example: when input arrives from communication line, it needs to be absorbed quickly to avoid retransmission n This requires a stack mechanism to save registers, etc.

21 Chapter 1 21 `Long` I/O n Normally I/O are very long with respect to I/O processing n In this case, the program and the CPU will have to wait even if there is concurrency between I/O and CPU processing

22 Chapter 1 22 Multiprogramming n Allows to achieve better use of I/O overlap times. n When a program reads a value on a I/O device it will need to wait s long time for the I/O operation to complete. u It can be difficult to use this waiting time. n So interrupts are mostly effective when a single CPU is shared among several concurrently active processes. n The CPU can then switch to execute another program when a program waits for the result of the read operation.

23 Chapter 1 23 I/O communication techniques n 3 techniques are possible for I/O operation (increasing sophistication) u Programmed I/O F Does not use interrupts: F CPU has to wait for completion of each I/O operation u Interrupt-driven I/O: CPU asks for I/O then continues F CPU can execute during I/O operation: F it gets interrupted when I/O operation is done F still, it has to transfer bytes from I/O to memory, so there is a slowdown (cycle stealing). u Direct Memory Access (DMA) F A block of data is transferred directly from/to memory without going through CPU¸ F But CPU will still have to be interrupted

24 Chapter 1 24 Programmed I/O n There is no interrupt, CPU is kept busy checking status of I/O module (polling or busy waiting). n No I/O overlap is possible n Only used in very simple machines.

25 Chapter 1 25 Interrupt-Driven I/O n CPU starts I/O then goes to other work n Processor is interrupted when I/O module ready to exchange data n No needless waiting n However every word read or written still passes through the CPU (cycle stealing) è CPU performance is affected by I/O

26 Chapter 1 26 Direct Memory Access n CPU issues request to a DMA module (separate module or incorporated into I/O module) n DMA module transfers a block of data directly to or from memory (without going through CPU) n An interrupt is sent when the task is complete n The CPU is only involved at the beginning and end of the transfer n The CPU is completely free to perform other tasks during data transfer

27 Chapter 1 27 MEMORY CHANNELS CPU Without DMA Direct Memory Access

28 Chapter 1 28 Cycle stealing n In general, when CPU and I/O operations must share physical components (bus, CPU, memory), I/O functions by occasionally stealing cycles from these components n When I/Os must pass through CPU (technique 2), the CPU must find the time to transfer bytes between I/O units and memory while it executes a program n Even in the case of DMA CPU and I/O share the memory, so the CPU can be delayed in its accesses to memory.

29 Chapter 1 29 Memory Hierarchy

30 Chapter 1 30 Cache Memory n Small cache of expensive but very fast memory interacting with slower but much larger memory n Invisible to OS and user programs but interact with other memory management hardware n Processor first checks if word referenced to is in cache n If not found in cache, a block of memory containing the word is moved to the cache

31 Chapter 1 31

32 Chapter 1 32 The Hit Ratio n Hit ratio = fraction of access where data is in cache n T1 = access time for fast memory n T2 = access time for slow memory n T2 >> T1 n When hit ratio is close to 1 the average access time is close to T1

33 Chapter 1 33 Locality of reference: a very important property of most programs n Memory references for both instruction and data tend to cluster over a long period of time. n Example: once a loop is entered, there is frequent access to a small set of instructions. Similarly, data is usually accessed in sequence. n Hence: once a word gets referenced, it is likely that nearby words will get referenced often in the near future. n Thus, the hit ratio will be close to 1 even for a small cache.

34 Chapter 1 34 Disk Cache (same principles) n A portion of main memory used as a buffer to temporarily to hold data for the disk n Locality of reference also applies here: once a record gets referenced, it is likely that nearby records will get referenced often in the near future. n If a record referenced is not in the disk cache, the sector containing the record is moved into the disk cache.

35 Chapter 1 35 Important concepts of Chapter 1 n Interrupts and how they work n 3 methods of I/O n simultaneity among I/O and CPU processing n memory hierarchy n cache memory n locality of reference

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