1. CS 1220 – Object Oriented Design 1 Project Info Term Project Overview 1.You need to read in a circuit description Consists of list of gates, what nodes (wire #) they connect to, and their delay 2.You create an internal (or in-memory) data structure which represents the circuit If a gate connects to wire#4, the gate object has a pointer to wire object #4 3.Read in a set of input tests We call those an input vector – it is simply the set of test conditions we want to exercise –At time=4, set input A to 1 4.Conduct simulation Will hopefully cause values to propagate to outputs 5.Visualize results is a console window or with wxWidgets 6.Repeat steps 3-6.

2. CS 1220 – Object Oriented Design 2 Project Info Term Project The digital logic can take on one of three values –0, 1, X –X means that the value is unknown This is different from Z, which means the gate is tri- stated and may be at some capacitive value between 0 and 1 We assume the gate will always drive either 0 or 1 (which is how they really behave), but X just means we can’t determine which value the gate is currently driving At time=0, all nodes (wires) are at unknown value (X) If an input changes, it will force the associated node to a particular value –Could be X

3. CS 1220 – Object Oriented Design 3 Project Info Term Project When parsing the circuit, we need to represent it as a data structure We need to develop an efficient data structure for the types of operations we need –What do we need to do? When a wire changes (capacitive) value, we need to send a message to all the gates with inputs connected to this wire that they need to recalculate their value When a gate recalculates and its output will be changing (after appropriate delay), it needs to notify the wire on its output to schedule a capacitive change –So, gates and wires need to know who is connected to them

4. CS 1220 – Object Oriented Design 4 Project Info Term Project The most straightforward data structure would be for the gate and wire classes to contain pointers to one another We should be able to create a data structure which reflects the inter-connections in the circuit Problem! Both classes refer to one another. Who gets included first? Use a forward declaration (in bold below). class Wire; class Gate { … private: Wire *in1, *in2; Wire *out; } class Gate; class Wire { … private: … vector out; }

5. CS 1220 – Object Oriented Design 5 Project Info Term Project So, how do we create and connect these Gates and Wires? –We will be parsing an input file that has lines like: NAND 5ns 2 4 6 –When we parse the keyword NAND, we know we need to create a new Gate of type NAND We also know we need to parse a string and 3 integers From the string you need to get rid of the “ns” and convert to an integer, then store the gate delay (hmmm, sounds like a variable for the Gate class) –The 3 integers get a bit tricky These are, in fact, Wire numbers

6. CS 1220 – Object Oriented Design 6 Project Info Term Project Parsing Wire numbers –When we encounter a Wire number in the circuit file, this may/may not be the first time that number has appeared –Consider Wire #2 from NAND 5ns 2 4 6 If the Wire #2 has not been seen before, we want to create a new Wire object, and somehow associate it with the #2 –Could be that Wire has a variable wireNum –Maybe better is that you keep track of all the Wires in the circuit in an array (or even better, a vector), and wireArray[2] contains a pointer to the Wire #2 –We create an object, put pointer to it in wireArray[2], and then connect the new Gate we are building to this wire. Also, we want to connect the wire to any gates it effects.

7. CS 1220 – Object Oriented Design 7 Project Info Term Project Consider Wire #2 from NAND 5ns 2 4 6 (cont) –If the Wire #2 has already been seen before, wireArray[2] won’t be NULL, and we can just connect this existing wire to the gate and the gate to this wire. So, as we parse a line, we create a Gate and any necessary Wires, and hook them up into the data structure!

8. CS 1220 – Object Oriented Design 8 Project Info Term Project Let’s think about the simulation We can accomplish it in two ways: clock-driven or event-driven –Clock driven Somewhat easier to reason about. Requires “visiting the past” to set present values. Harder to determine when the simulation terminates. More costly in terms of execution time. –Event-Driven Events occur at specific times As you handle events they may generate future events The simulation ends naturally when there are no future events. Less costly simulation method. Specifically, a Wire changing value (event) will cause a Gate to re- evaluate –If the Gate changes value, it will schedule a future event (its output Wire changes value) after the appropriate time delay Need a way of storing future events –We use a priority queue You can just use the one from STL

9. CS 1220 – Object Oriented Design 9 Project Info Term Project In either model, your simulation is a big loop –You either advance time (clock-driven) or pull an event off the queue (event driven) and the update the necessary gates. Note, under event-driven simulation, time is updated to the time the most recent event occurred In the clock-driven model –Gates send messages to Wires (update your value for time t) In the event-driven model –Wire sends messages to Gates (I’ve updated, does this cause you to change your output) If the Gates change output value, they schedule an event in the future (currentTime + delayTime) and put this event on the queue If an Output Pad receives a message, it needs save this info for history Outputs don’t generate new events –Simulation continues until queue is empty How does the queue get events in it to start with?

10. CS 1220 – Object Oriented Design 10 Project Info Term Project Ahhhh, that’s where the Vector file comes in –You need to parse lines like: INPUT inA 0 1 At time 0, inA takes value of 1 –Since inA has a Wire associated with it, this wire will have a value change at time 0 So, you just put this event in the queue –But what Wire is associated with inA? You parsed that with the Circuit file! INPUT inA 5 means inA connects to Wire #5 You need some kind of data structure to associate Wires and Input Pads

11. CS 1220 – Object Oriented Design 11 Project Info Term Project Big picture –Parse Circuit file to create data structures –Clock-driven Model Parse Vector file to put initial values on the wires Run the clock until some suitable time (e.g., 60 seconds) –Event-driven Model Parse Vector file to put initial values in queue Run simulation until the queue runs dry (or for 60 seconds) –As info hits Output gates, store this output information One other item: 3-value logic –You circuit should be initialized with all Wires having value X –The input vectors will then slowly cause the X’s to be replaced by real values