Download presentation
Presentation is loading. Please wait.
1
ECE555 Lecture 10 Nam Sung Kim University of Wisconsin – Madison
Dept. of Electrical & Computer Engineering
2
Outline Multiplier Shifter Datapath Bitslice Organization
Array Multiplier CSA/Wallace Tree Multiplier Shifter Datapath Bitslice Organization
3
Multiplication Example
4
Multiplication Example
5
Multiplication Example
6
Multiplication Example
7
Multiplication Example
8
Multiplication Example
9
Multiplication Example M x N-bit multiplication
Produce N M-bit partial products Sum these to produce M+N-bit product
10
General Multiplication Form
Multiplicand: Y = (yM-1, yM-2, …, y1, y0) Multiplier: X = (xN-1, xN-2, …, x1, x0) Product:
11
Dot Diagram Each dot represents a bit (or partial product)
12
Array Multiplier
13
Rectangular Array Squash array to fit rectangular floorplan
14
Wallace Tree Multiplier
Using 3:2 compressor (FA!) 6 5 4 3 2 1 6 5 4 3 2 1 x0 x3 6 5 4 3 2 1 6 5 4 3 2 1
15
Wallace Tree Multiplier
Using 3:2 compressor (FA!) x0y3 x0y2 x0y1 x0y0 x1y3 x1y2 x1y1 x1y0 + x2y3 x2y2 x2y1 x2y0 + + x3y3 x3y2 x3y1 x3y0
16
Wallace Tree Multiplier
Using 3:2 compressor (FA!) x0y2 x0y1 x0y0 x1y0 x2y2 x2y1 + + x3y3 x3y1 x3y0 + x1y1 x3y2 x0y3 + + + + x2y3 x1y3 x1y2 x2y0
17
Wallace Tree Multiplier
18
Parallel Programmable Shifters
Shift amount Shift direction Shift type (logical, arith, circular) Control = Data Out Data In Shifting a data word left or right over a constant amount is a trivial hardware operation and is implemented by the appropriate signal wiring Shifters used in multipliers, floating point units Consume lots of area if done in random logic gates
19
A Programmable Binary Shifter
rgt nop left Ai Ai-1 rgt nop left Bi Bi-1 A1 A0 1 Ai Bi For class handout Ai-1 Bi-1
20
A Programmable Binary Shifter
rgt nop left Ai Ai-1 rgt nop left Bi Bi-1 A1 A0 1 Ai Bi For lecture Ai-1 Bi-1
21
4-bit Barrel Shifter Area dominated by wiring Example: Sh0 = 1
B3B2B1B0 = A3A2A1A0 Sh1 = 1 B3B2B1B0 = A3A3A2A1 Sh2 = 1 B3B2B1B0 = A3A3A3A2 Sh3 = 1 B3B2B1B0 = A3A3A3A3 B3 Sh1 A2 B2 Sh2 A1 B1 Sh3 For class handout A0 B0 Area dominated by wiring Sh0 Sh1 Sh2 Sh3
22
4-bit Barrel Shifter Area dominated by wiring Example: Sh0 = 1
B3B2B1B0 = A3A2A1A0 Sh1 = 1 B3B2B1B0 = A3A3A2A1 Sh2 = 1 B3B2B1B0 = A3A3A3A2 Sh3 = 1 B3B2B1B0 = A3A3A3A3 B3 Sh1 A2 B2 Sh2 A1 B1 Sh3 For lecture Number of rows equals the word length of the data and the number of columns equals the maximum shift width. The control wires are routed diagonally through the array. Implementation does sign extend – so arithmetic shift. Note that signal goes through at most one fet (so constant propagation delay (in theory)) Also note, that the capacitance of the output wires goes linearly with the shift width (linear grow in fet diffusion capacitance). But note the N**2 increase in diff cap load on the input data lines (for circular shifter) Size of cell bounded by the pitch of the metal wires. Also not the n! diffusion capacitances on the input lines Need shift control (encoded) count decoded into shift signals since it needs a control wire for every shift bit. Since count is normally provided in an encoded form, also need to have a decoder.. A0 B0 Area dominated by wiring Sh0 Sh1 Sh2 Sh3
23
4-bit Barrel Shifter Layout
Widthbarrel Only one Sh# active at a timel Widthbarrel ~ 2 pm N N = max shift distance, pm = metal pitch Delay ~ 1 fet + N diff caps
24
8-bit Logarithmic Shifter
For class handout B0 A0
25
8-bit Logarithmic Shifter
1 Sh1 !Sh1 Sh2 !Sh2 Sh3 !Sh3 A3 B3 A2 B2 A1 B1 For lecture Total shift is decomposed into shifts over powers of two. A shifter of width of N consists of log2N stages where the ith stage either shifts over 2^i or passes the data unchanged. Note that the control bits are encoded – thus we don’t need a decoder for the shift count (as in the previous shifter). The speed depends on the shift width in a logarithmic way – and B0 A0 log N stages
26
8-bit Logarithmic Shifter Layout
1 2 4 A3 B3 A2 B2 A1 B1 A0 Notice regularity of layout M K 2**K 1 0 1 2 1 2 4 2 4 8 3 8 B0 Widthlog ~ pm(2K+(1+2+…+2K-1)) = pm(2K+2K-1) K = log2 N Delay ~ K fets + 2 diff caps
27
Datapath Bit-Sliced Organization
Control Flow Bit 0 Bit 1 Bit 2 Bit 3 From I$ Pipeline Register Register File Multiplexer Pipeline Register Multiplexer Adder Shifter Pipeline Register Pipeline Register decoder Data Flow To/From D$ Tile identical bit-slice elements
Similar presentations
![Modelagem Básica Entity –Exemplos: entity identifier is [ port (port_interface_list);] {entity_declarative_item} end [entity] [identifier]; Interface_list.](/2/352417/big_thumb.jpg "Modelagem Básica Entity –Exemplos: entity identifier is [ port (port_interface_list);] {entity_declarative_item} end [entity] [identifier]; Interface_list.>")
