ECE555 Lecture 8/9 Nam Sung Kim University of Wisconsin – Madison

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ECE555 Lecture 8/9 Nam Sung Kim University of Wisconsin – Madison
Dept. of Electrical & Computer Engineering

Outline Adder Carry Ripple Manchester Carry Carry Bypass (or Skip)
Carry Select Paralle Prefix Brent-Kung Kogge-Stone Delay and Power Comparisons

Single-Bit Addition Half Adder Full Adder A B Cout S 1 A B C Cout S 1

Single-Bit Addition Half Adder Full Adder A B Cout S 1 A B C Cout S 1

PGK For a full adder, define what happens to carries
Generate: Cout = 1 independent of C G = Propagate: Cout = C P = Kill: Cout = 0 independent of C K =

PGK For a full adder, define what happens to carries
Generate: Cout = 1 independent of C G = A • B Propagate: Cout = C P = A  B Kill: Cout = 0 independent of C K = ~A • ~B Co(G,P) = G+PCi S(G,P) = P  Ci

Full Adder Design I Brute force implementation from eqns
S=ABCi+ABCi+ABCi+ABCi = Ci (AB+AB)+Ci (AB+AB) Co=AB+BCi+ACi=(AB+BCi+Aci)

Full Adder Design II Factor S in terms of Co
S = ABCi + (A + B + Ci)(~Co) Critical path is usually Ci to Co in ripple adder B A Ci !Co !S 2 3 6 4 4 8 Co S

Identical Delays for Carry and Sum
Full Adder Design III B !B !P Identical Delays for Carry and Sum Cin Cin B A !B P P !P S Cin P !Cout !Cout P A P !P !P Sum generation Carry generation Signal set-up

Critical path goes from Ci to Co Design full adder to have fast carry delay Worst case delay linear with the number of bits td = O(N) tadder = (N-1)tcarry + tsum

Inversion Property

Mirror Adder Critical path passes through majority gate
Built from minority + inverter Eliminate inverter and use inverting full adder

Mirror Adder Cell B A Ci !Co !S 2 3 6 4 4 8

Fast Carry Chain Design
The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generated Gi = Ai & Bi = AiBi propagated Pi = Ai  Bi (sometimes use Ai | Bi) annihilated (killed) Ki = !Ai & !Bi Giving a carry recurrence of Ci+1 = Gi | PiCi C1 = C2 = C3 = C4 =

Fast Carry Chain Design
The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generated Gi = Ai & Bi = AiBi propagated Pi = Ai  Bi (sometimes use Ai | Bi) annihilated (killed) Ki = !Ai & !Bi Giving a carry recurrence of Ci+1 = Gi | PiCi C1 = G0 | P0C0 C2 = G1 | P1G0 | P1P0 C0 C3 = G2 | P2G1 | P2P1G0 | P2P1P0 C0 C4 = G3 | P3G2 | P3P2G1 | P3P2P1G0 | P3P2P1P0 C0

Manchester Carry Chain
Switches controlled by Gi and Pi Total delay of time to form the switch control signals Gi and Pi setup time for the switches signal propagation delay through N switches in the worst case !Ci+1 !Ci Gi Pi clk

4-bit Sliced MCC Adder     A3 B3 A2 B2 A1 B1 A0 B0 clk G P G P G P
&  &  &  &  G P G P G P G P !C4 !C0 !C3 !C2 !C1 S3 S2 S1 S0

Domino Manchester Carry Chain Circuit
clk P3 P2 P1 P0 1 2 3 4 Ci,4 !(G3 | P3G2 | P3P2G1 | P3P2P1G0 | P3P2P1P0 Ci,0) !(G2 | P2G1 | P2P1G0 | P2P1P0 Ci,0) !(G1 | P1G0 | P1P0 Ci,0) !(G0 | P0 Ci,0) G3 G2 G1 G0 Ci,0 1 2 2 3 3 4 4 5 5 6 clk

Ci,0 FA A1 B1 S1 A2 B2 S2 A3 B3 S3 Co,3 Co,3 BP = P0 P1 P2 P3 “Block Propagate” If (P0 & P1 & P2 & P3 = 1) then Co,3 = Ci,0 otherwise the block itself kills or generates the carry internally

Carry-Skip Chain Implementation
block carry-out carry-out BP block carry-in Cin G0 P0 P1 P2 P3 G1 G2 G3 !Cout BP

bits 12 to 15 bits 8 to 11 bits 4 to 7 bits 0 to 3 Setup Setup Setup Setup Carry Propagation Carry Propagation Carry Propagation Carry Propagation Ci,0 Sum Sum Sum Sum Worst-case delay  carry from bit 0 to bit 15 = carry generated in bit 0, ripples through bits 1, 2, and 3, skips the middle two groups (B is the group size in bits), ripples in the last group from bit 12 to bit 15 Tadd = tsetup + B tcarry + ((N/B) -1) tskip +(B -1)tcarry + tsum

Carry Select Adder 4-b Setup “0” carry propagation
1 multiplexer Cin Cout Sum generation P’s G’s C’s Precompute the carry out of each block for both carry_in = 0 and carry_in = 1 (can be done for all blocks in parallel) and then select the correct one S’s

bits 12 to 15 bits 8 to 1 bits 4 to 7 bits 0 to 3 A’s B’s A’s B’s A’s B’s A’s B’s Setup Setup Setup Setup P’s G’s P’s G’s P’s G’s P’s G’s “0” carry “0” carry “0” carry “0” carry “1” carry “1” carry “1” carry “1” carry 1 mux mux mux mux Cout Cin C’s C’s C’s C’s Sum gen Sum gen Sum gen Sum gen S’s S’s S’s S’s

bits 12 to 15 bits 8 to 1 bits 4 to 7 bits 0 to 3 A’s B’s A’s B’s A’s B’s A’s B’s 1 Setup Setup Setup Setup P’s G’s P’s G’s P’s G’s P’s G’s “0” carry “0” carry “0” carry “0” carry +4 “1” carry “1” carry “1” carry “1” carry 1 +1 +1 +1 +1 mux mux mux mux Cout Cin C’s C’s C’s C’s Sum gen Sum gen Sum gen Sum gen S’s S’s S’s S’s Tadd = tsetup + B tcarry + N/B tmux + tsum

bits 14 to 19 bits 9 to 13 bits 5 to 8 bits 2 to 4 bits 0 to 1 A’s B’s A’s B’s A’s B’s A’s B’s A’s B’s Setup Setup Setup Setup Setup P’s G’s P’s G’s P’s G’s P’s G’s P’s G’s “0” carry “0” carry “0” carry “0” carry “0” carry 1 “1” carry “1” carry “1” carry “1” carry “1” carry mux Cout mux mux mux mux Cin C’s C’s C’s C’s C’s Sum gen Sum gen Sum gen Sum gen Sum gen S’s S’s S’s S’s S’s

bits 14 to 19 bits 9 to 13 bits 5 to 8 bits 2 to 4 bits 0 to 1 A’s B’s A’s B’s A’s B’s A’s B’s A’s B’s 1 Setup Setup Setup Setup Setup P’s G’s P’s G’s P’s G’s P’s G’s P’s G’s “0” carry “0” carry “0” carry “0” carry “0” carry +2 +6 +5 +4 +3 “1” carry 1 “1” carry “1” carry “1” carry “1” carry +1 +1 +1 +1 +1 Cout mux mux mux mux mux Cin C’s C’s C’s C’s C’s +1 Sum gen Sum gen Sum gen Sum gen Sum gen S’s S’s S’s S’s S’s Tadd = tsetup + 2 tcarry + √N tmux + tsum

Define carry operator on (G,P) signal pairs is associative, i.e., [(g’’’,p’’’) (g’’,p’’)] (g’,p’) = (g’’’,p’’’) [(g’’,p’’) (g’,p’)] (G’’,P’’) (G’,P’) where G = G’’  P’’G’ P = P’’P’ (G,P)

(Gi:j,Pi:j) = (Gi:k+Pi:k∙Gk-1:j, Pi:k∙Pk-1:j)

Co,0 = G0+P0Ci,0 Co,1 = G1+P1Co,0 = G1 +P1(G0+P0Ci,0) = G1 +P1G0+P1P0Ci,0 = [G1+ P1G0]+[P1P0 ]Ci,0 = G1:0+P1:0 Ci,0 Co,2 = G2 +P2Co,1 Co,3 = G3 +P3Co,2 = G3 +P3(G2 +P2Co,1) = G3 +P3G2 +P3P2Co,1) = [G3 +P3G2 ]+ [P3P2]Co,1 = G3:2+P3:2 Co,1 = G3:2+P3:2 (G1:0+P1:0 Ci,0) = [G3:2+P3:2 G1:0]+[P3:2 P1:0 ]Ci,0) = G3:0+P3:0Ci,0

(G0,P0) ■ (G1,P1) ■ (G2,P2) ■ … ■ (GN-2,PN-2) ■ (GN-1,PN-1)
PPA General Structure Given P and G terms for each bit position, computing all the carries is equal to finding all the prefixes in parallel (G0,P0) ■ (G1,P1) ■ (G2,P2) ■ … ■ (GN-2,PN-2) ■ (GN-1,PN-1) Since is associative, we can group them in any order but note that it is not commutative Measures to consider number of cells tree cell depth (time) tree cell area cell fan-in and fan-out max wiring length wiring congestion delay path variation (glitching) Pi, Gi logic (1 unit delay) Ci parallel prefix logic tree (1 unit delay per level) Si logic (1 unit delay)

Parallel Prefix Computation
Brent-Kung PPA G15 p15 A = 2log2N A = N/2 G14 p14 G13 p13 G12 P12 G11 p11 G10 P10 G9 p9 G8 P8 G7 P7 G6 P6 G5 P5 G4 P4 G3 P3 G2 p2 G1 P1 G0 P0 Cin T = log2N Parallel Prefix Computation T = log2N - 2 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1

Parallel Prefix Computation
Brent-Kung PPA G15 p15 A = 2log2N A = N/2 G14 p14 G13 p13 G12 P12 G11 p11 G10 P10 G9 p9 G8 P8 G7 P7 G6 P6 G5 P5 G4 P4 G3 P3 G2 p2 G1 P1 G0 P0 Cin T = log2N Parallel Prefix Computation T = log2N - 2 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1

A = log2N A = N G14 P14 G13 P13 G12 P12 G11 P11 G10 P10 G9 P9 G8 P8 G7 P7 G6 P6 G5 P5 G4 P4 G3 P3 G2 P2 G1 P1 G0 P0 Cin T = log2N Parallel Prefix Computation C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 Tadd = tsetup + log2N t + tsum