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EE 5301 – VLSI Design Automation I

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1 EE 5301 – VLSI Design Automation I
EE 5301 – VLSI Design Automation I Part I: Introduction Kia Bazargan University of Minnesota Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

2 Administrative Issues
Administrative Issues Class Time and venue: ___________________________ Web page: (required x.500 ID & pwd) !!!! Check the class web page & discussion group regularly !!!! Textbook: S. H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons, 1999. Grades 40% homework and projects 15% quizzes 20% midterm – open book. Date: ________________ 25% Final exam – open book Date: ______________________________ Check out the web page regularly! Handouts will be distributed in class (off-site students can download from the web page) Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

3 Administrative Issues (cont.)
Personnel Instructor: Kia Bazargan Phone: (612) Office: EE/CSci 4-159 Office hours: ________________________ TA: ___________________ ___________________________ Phone: _____________________________ Office: ______________________________ Office hours: __________________________ Fall 2003 EE VLSI Design Automation I

4 Administrative Issues (cont.)
Policies Homework must be received before the class 1min – 24 hours late: 50% of the grade > 24 hours late: 0% Zero tolerance for cheating Collaboration OK, copying NOT OK Include ID on all homework, exams, etc. No extra work for extra credit Check the class web pages regularly, the students are responsible for checking the discussion threads and announcements regularly Subscribe to the class mailing list Fall 2003 EE VLSI Design Automation I

5 This is a sample text, not printed, but animated
Online Slides Slides are posted on the web Handouts as .pdf file Powerpoint slides provided too NOTE: some slides are animated (like this one) Click on the slide to see the animation Click once more. Note: some slides have notes! (like this one) Some slides contain text that is not printed in the handouts, but animated. These are left for you to fill out in the handouts. An example is shown below (animated: click to see) Slide “notes” can be found here. You might need to scroll to read the entire text. Some slides are animated. Click on each slide before advancing to the next one to see the animation (if any). This is a sample text, not printed, but animated Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

6 References and Copyright
Textbooks referred (none required) [Mic94] G. De Micheli “Synthesis and Optimization of Digital Circuits” McGraw-Hill, 1994. [CLR90] T. H. Cormen, C. E. Leiserson, R. L. Rivest “Introduction to Algorithms” MIT Press, 1990. [Sar96] M. Sarrafzadeh, C. K. Wong “An Introduction to VLSI Physical Design” McGraw-Hill, 1996. [She99] N. Sherwani “Algorithms For VLSI Physical Design Automation” Kluwer Academic Publishers, 3rd edition, 1999. Fall 2003 EE VLSI Design Automation I

7 References and Copyright (cont.)
Slides used: (Modified by Kia when necessary) [©Sarrafzadeh] © Majid Sarrafzadeh, 2001; Department of Computer Science, UCLA [©Sherwani] © Naveed A. Sherwani, (companion slides to [She99]) [©Keutzer] © Kurt Keutzer, Dept. of EECS, UC-Berekeley [©Gupta] © Rajesh Gupta UC-Irvine Fall 2003 EE VLSI Design Automation I

8 What is This Course All About?
What is This Course All About? Prerequisite C / C++ programming experience What is covered? Basic algorithms, complexity theory Integrated circuit (IC) Design flow Computer Aided Design (CAD) tool development for Very Large Scale Integration (VLSI) Lots of programming! Next slides: Overview of IC design steps Related courses at U of M Outline of this course Combination of algorithmic / structural / gate-level optimization are used Emphasis on performance Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

9 The Inverted Pyramid Electronic Systems > $1 Trillion
Semiconductor > $220 B CAD $3 B Fall 2003 EE VLSI Design Automation I [©Keutzer]

10 EE 5301 - VLSI Design Automation I
IC Products Processors CPU, DSP, Controllers Memory chips RAM, ROM, EEPROM Analog Mobile communication, audio/video processing Programmable PLA, FPGA Embedded systems Used in cars, factories Network cards System-on-chip (SoC) Datapath is the “computational unit” of a processor Digital Signal Processing (DSP) chips are used all over the place: audio, image processing, satellite applications, etc. Memory performance always behind CPU speed, greater need for more capacity, bandwidth Network processors: low-cost, versatile, fast designs needed for the increasing internet applications, protocols, etc. Images: amazon.com Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

11 IC Product Market Shares
Source: Electronic Business Fall 2003 EE VLSI Design Automation I

12 Semiconductor Industry Growth Rates
Source: (McClean Report) Fall 2003 EE VLSI Design Automation I

13 Source: http://www.edat.com/edac
More Demand for EDA CAE = Computer Aided Engineering Source: Fall 2003 EE VLSI Design Automation I

14 Source: http://www.edat.com/edac
Growth in System Size CAGR = Compound Annual Growth Rate Source: Fall 2003 EE VLSI Design Automation I

15 Example: Intel Processor Sizes
Silicon Process Technology Intel386TM DX Processor Intel486TM DX Pentium® Processor Pentium® Pro & Pentium® II Processors Source: Fall 2003 EE VLSI Design Automation I

16 EE 5301 - VLSI Design Automation I
Moore’s Law Transistors Microprocessors PPC603 1 10 100 1K 10K 100K 1M 10M Pentium Pentium Pro 80486 68040 PPC601 80386 MIPS R4000 68000 68020 8086 4004 8080 10x/6 years 1975 1980 1985 1990 1995 Fall 2003 EE VLSI Design Automation I [©Keutzer]

17 NRTS: Chip Frequencies
Clock speed GHz 11 9 7 5 3 1 1997 1999 2001 2003 2006 2009 2012 On-chip, local clock, high performance On-chip, global clock, high performance Fall 2003 EE VLSI Design Automation I [©Keutzer]

18 Increasing Device and Context Complexity
Exponential increase in device complexity Increasing with Moore's law (or faster)! More complex system contexts System contexts in which devices are deployed (e.g. cellular radio) are increasing in complexity Require exponential increases in design productivity Complexity We have exponentially more transistors! Fall 2003 EE VLSI Design Automation I [©Keutzer]

19 Deep Submicron Effects
Smaller geometries are causing a wide variety of effects that we have largely ignored in the past: Cross­coupled capacitances Signal integrity Resistance Inductance DSM Effects Design of each transistor is getting more difficult! Fall 2003 EE VLSI Design Automation I [©Keutzer]

20 Heterogeneity on Chip Greater diversity of on­chip elements Processors
Software Memory Analog Heterogeneity More transistors doing different things! Fall 2003 EE VLSI Design Automation I [©Keutzer]

21 Stronger Market Pressures
Decreasing design window Less tolerance for design revisions Time-to-market Exponentially more complex, greater design risk, greater variety, and a smaller design window! Fall 2003 EE VLSI Design Automation I [©Keutzer]

22 EE 5301 - VLSI Design Automation I
A Quadruple­Whammy Complexity Time-to-market Heterogeneity DSM Effects Fall 2003 EE VLSI Design Automation I [©Keutzer]

23 Role of EDA: close the productivity gap
How Are We Doing? Logic transistors per chip (K) 10 100 1,000 10,000 100,000 1,000,000 10,000,000 Logic Tr./Chip Trans. / Staff . Month Productivity 10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Tr./S.M 58% / Yr. compound complexity growth rate Productivity gap 21% / Yr. compound productivity growth rate 1981 1985 1989 1993 1997 2001 2005 2009 Source: SEMATECH Role of EDA: close the productivity gap Fall 2003 EE VLSI Design Automation I [©Keutzer]

24 Evolution of the EDA Industry
What’s next? Results (design productivity) Synthesis – Cadence, Synopsys Schematic entry – Daisy, Mentor, Valid Transistor entry – Calma, Computervision, Magic Effort (EDA tool effort) McKinsey S-Curve Fall 2003 EE VLSI Design Automation I [©Keutzer]

25 IC Design Steps (cont.) High-level Description Functional Description
IC Design Steps (cont.) High-level Description Functional Description Specifications Behavioral VHDL, C Structural VHDL These steps are not etched in stone: there are lots of varieties High-level description defines major components of the design and their interaction Functional description is usually at Register Transfer Level (RTL). RTL description deals with more details, lists signals, block components. Languages such as VHDL are used to describe the architecture. Fall 2003 EE VLSI Design Automation I Figs. [©Sherwani] VLSI Design Automation I – © Kia Bazargan

26 IC Design Steps (cont.) Synthesis Physical Design Technology Mapping
IC Design Steps (cont.) High-level Description Functional Description Specifications Logic Description Synthesis Physical Design Technology Mapping Placed & Routed Design Gate-level Design Again, these steps are not etched in stone: there are lots of varieties Logic description is usually generated by Computer Aided Design (CAD) tools Gate-level design (also known as “netlist”) describes the design in the atomic entities of the technology. For a CMOS design, transistors are used. In an FPGA design, look-up tables (LUTs) are used. The process of converting a logic description to a gate-level design is called technology mapping. There are a *lot* of optimizations involved after technology mapping We might go back and forth between these steps (e.g., after gate-level desc., we might simulate and find bugs => go back to RTL or high-level description and fix the bug) I haven’t shown testing/verification This course helps you understand the methods and algorithms used for automatic high-level synthesis and and physical design You will develop small CAD tools that do these steps automatically. Fabri- cation X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Packaging Fall 2003 EE VLSI Design Automation I Figs. [©Sherwani] VLSI Design Automation I – © Kia Bazargan

27 The Big Picture: IC Design Methods
The Big Picture: IC Design Methods Cost / Development Time Design Methods Quality # Companies involved Full Custom Standard Cell Library Design What is the difference between full custom and ASIC design? Tools used in Full Custom would be Magic-like, and tools used in RTL-Level Design would be CAD tools for synthesis, physical design, etc. Since Full Custom costly (number of designers, design time, fabrication cost, scalability, etc.) only companies like Intel afford This course will cover the underlying theory for the tools that are used mostly in the last two methods. ASIC – Standard Cell Design RTL-Level Design Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

28 Optimization: Levels of Abstraction
Algorithmic Encoding data, computation scheduling, balancing delays of components, etc. Gate-level Reduce fan-out, capacitance Gate duplication, buffer insertion Layout / Physical-Design Move cells/gates around to shorten wires on critical paths Abut rows to share power / ground lines Effectiveness Level of detail Fall 2003 EE VLSI Design Automation I

29 Layouts [© Prentice Hall]
Full Custom Design Component Design Structural/RTL Description Mem Ctrl Comp. Unit Reg File Place & Route A/D PLA I/O comp RAM A team of engineers work on each component of the system After each component is designed / tested / optimized, put together the whole thing Automatic tools might be used in each of the stages ... Floorplan [©Sherwani] Layouts [© Prentice Hall] Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

30 Full Custom Design Example
Full Custom Design Example I/O Pad Via comp PLA Metal2 Macro cell design I/O Metal1 RAM A/D Some wires occupy “metal layer 1”, and the others occupy “metal layer 2” Some components are designed manually (e.g., the “comp” unit that hosts functional components) to achieve the best speed, and some components are designed in standard-cell (we will see an example of standard cell in the next slides) to save time. Glue logic (standard cell design) [©Sherwani] Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

31 EE 5301 - VLSI Design Automation I
ASIC Design Structural/ RTL Description Mem Ctrl Comp. Unit Reg File HDL Programming P_Inp: process (Reset, Clock) begin if (Reset = '1') then sum <= ( others => '0' ); input_nums_read <= '0'; sum_ready <= '0'; add82 : kadd8 port map ( a => add_i1, b => add_i2, ci => carry, s => sum_o); Mult_i1 <= sum_o(7 downto 0); D C B A Designers describe the hardware in high-level languages such as VHDL and Verilog A lot of automation is used (and the quality of the chip won’t be as good as full-custom – maybe up to 20x worse) The cell library is developed by CAD companies. It contains gates such as AND, OR, XOR, or could even offer more complex cells such as adders and multipliers. C D A B Cell library Floorplan [©Sherwani] Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

32 ASIC (Standard Cell) Design Example
ASIC (Standard Cell) Design Example Cell Feedthrough GND VDD Metal1 Metal2 D C B A C D A B Cell library Note the “standard” layout of the cells, which in turn makes the placement of the cells and routing of the nets (wires that connect cells) easier. Also note that all horizontal wires are routed on one metal layer, and all vertical ones are routed on the other metal layer. Note how power (VDD) and ground are routed The routing is mostly done in the “channels” between cells, with the occasional of using “feedthrough” cells to connect different channels. Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

33 Where Is This Course in the Big Picture?
Where Is This Course in the Big Picture? VLSI related courses: VLSI CAD VLSI Design Others EE 5301 VLSI Design Automation I EE 5302 Automation II EE 5323 VLSI Design I EE 5324 VLSI Design II EE 4301 Digital Design With Programmable Logic EE 5329 VLSI Digital Signal Processing Systems The VLSI CAD courses cover algorithms that are used in CAD tools (used in ASIC designs) The VLSI Design courses deal with the full-custom methodology EE 5333 Analog Integrated Circuit Design EE 5549 Digital Signal Processing Structures for VLSI Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

34 EE 5301 - VLSI Design Automation I
Course Outline Basic algorithms and complexity theory Circuit representations Classes of problems (P, NP) Classes of algorithms (dynamic programming, network flow, greedy, linear programming, etc.) Graph algorithms High-level synthesis Converting high-level languages to RTL Scheduling operations Allocating functional resources (adders, multipliers, registers, etc.) Register minimization Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

35 EE 5301 - VLSI Design Automation I
Course Outline (cont.) Partitioning FM, KL, hMetis algorithms Floorplanning Slicing, non-slicing floorplans Simulated annealing floorplanning algorithms Placement / Packing Force-directed Simulated annealing Quadratic placement Global / detailed routing Maze routing, line-search, Steiner trees, channel routing, Fall 2003 EE VLSI Design Automation I VLSI Design Automation I – © Kia Bazargan

36 EE 5301 - VLSI Design Automation I
To Probe Further... International Technology Roadmap for Semiconductors (ITRS) SEMATECH The EDA Consortium's 2001 Forecast Panel Textbook Chapters 1, 2 Fall 2003 EE VLSI Design Automation I

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