1. EEL4712 Digital Design
(Midterm 2 Review)

2. Arrays
Write a VHDL type declaration called MY_ARRAY that creates a 2D array with 8 rows and 4 columns, where each element is a 32-bit std_logic_vector.
type my_array is array (0 to 7, 0 to 3) of std_logic_vector (31 downto 0);

3. Arrays
Write a VHDL type declaration called MY_ARRAY that creates a 2D array with unconstrained ranges for each dimension, where each element is a 32-bit std_logic_vector.
Type my_array is array (natural range <>, natural range <>) of std_logic_vector (31 downto 0);

4. Arrays
Using the type from part b, instantiate an object of type MY_ARRAY with 50 rows and 100 columns.
Signal my_array (0 to 49, 0 to 99);

5. Arrays What doesn’t VHDL allow in the following type declaration?
type MY_ARRAY is array (natural range<>, natural range<>) of std_logic_vector
Since it does not allow unconstrainted arrays of unconstrainted types

6. FPGA Fabric
What is the maximum number of gates that can be implemented in a 3-input, 2-output LUT?
There is no maximum

7. FPGA Fabric
What are the components in an FPGA used for reconfigurable interconnect?
Routing tracks
Connection boxes
Switch boxes
Routing tracks
CLB
CLB
CLB
CLB
CLB
CLB

8. FPGA Fabric
Show the sequence of FPGA resources that stablish a connection between two CLBs that are placed far apart on the FPGA
CLB -> Connection Box ->
routing track -> switching box -> routing tracks -> (it may repeated)
Connection box -> CLB

9. Technology Mapping

10. FSMD
Create an FSMD that implements the following pseudo‐code.

11. References
Read chapters 8 and 10 of the book

12. Questions?