1. Chapter 5 Passive and Active Current Mirrors
5.1 Basic Current Mirrors
Design issues
Voltage headroom. ( 0 for ideal current source )
Output impedance. ( for ideal current source )
Supply, process, and temperature dependence.
Matching
If the gate-source voltage of a MOSFET is precisely defined, then its drain current is not. → Copying currents from a reference.
𝐼 𝑜𝑢𝑡 ≈ 1 2 𝜇 𝑛 𝐶 𝑜𝑥 𝑊 𝐿 𝑅 2 𝑅 1 + 𝑅 2 𝑉 𝐷𝐷 − 𝑉 𝑇𝐻 2
Depending on supply, process, and temperature.
The threshold voltage may vary by 100 mV from wafer to wafer.
Both μn and VTH exhibit temperature dependence.
The issue becomes more severe as the device is biased with a smaller overdrive voltage. VTH variations  larger % variations on Iout.
Chung-Yu (Peter) Wu 2016

2. Chapter 5 Passive and Active Current Mirrors
5.1 Basic Current Mirrors
For Iout = IREF
It allows precise copying of the current with no dependence on process and temperature.
Current mirrors employ the same length for all of the transistors so as to minimize errors due to the side diffusion of the source and drain areas.
Current ratio by only scaling the width of transistors.
𝑉 𝐺𝑆 = 𝑓 −1 𝐼 𝑅𝐸𝐹
𝑓𝑓 −1 𝐼 𝑅𝐸𝐹 = 𝐼 𝑅𝐸𝐹
𝐼 𝑅𝐸𝐹 = 1 2 𝜇 𝑛 𝐶 𝑜𝑥 𝑊 𝐿 𝑉 𝐺𝑆 − 𝑉 𝑇𝐻 2 　　 𝐼 𝑜𝑢𝑡 = 1 2 𝜇 𝑛 𝐶 𝑜𝑥 𝑊 𝐿 𝑉 𝐺𝑆 − 𝑉 𝑇𝐻 2 　　 𝐼 𝑜𝑢𝑡 𝐼 𝑅𝐸𝐹 = 𝑊 𝐿 𝑊 𝐿 1
𝐿 𝑒𝑓𝑓 = 𝐿 𝑑𝑟𝑎𝑤𝑛 −2 𝐿 𝐷
Chung-Yu (Peter) Wu 2016

3. Chapter 5 Passive and Active Current Mirrors
5.2 Cascode Current Mirror
Channel length modulation effect results in significant error in copying currents.
As 　　　　　　　　　　　, for ID1 = ID2 , VDS1 must be equal to VDS2 .
Vb is chosen such that VY = VX if then VGS0 = VGS3 and VX = VY
Such accuracy is obtained at the cost of the voltage headroom consumed by M3.
𝐼 𝐷1 = 1 2 𝜇 𝑛 𝐶 𝑜𝑥 𝑊 𝐿 𝑉 𝐺𝑆 − 𝑉 𝑇𝐻 𝜆 𝑉 𝐷𝑆1 　　 𝐼 𝐷2 = 1 2 𝜇 𝑛 𝐶 𝑜𝑥 𝑊 𝐿 𝑉 𝐺𝑆 − 𝑉 𝑇𝐻 𝜆 𝑉 𝐷𝑆2
𝐼 𝐷2 𝐼 𝐷1 = 𝑊 𝐿 𝑊 𝐿 𝜆 𝑉 𝐷𝑆2 1+𝜆 𝑉 𝐷𝑆1
𝑉 𝑏 − 𝑉 𝐺𝑆3 = 𝑉 𝑌
𝑉 𝑏 = 𝑉 𝐺𝑆3 + 𝑉 𝑌
𝑉 𝑁 = 𝑉 𝐺𝑆0 + 𝑉 𝑋 = 𝑉 𝑏
𝑊 𝐿 𝑊 𝐿 0 = 𝑊 𝐿 𝑊 𝐿 1
Chung-Yu (Peter) Wu 2016

4. Chapter 5 Passive and Active Current Mirrors
5.2 Cascode Current Source
𝑉 𝐺𝑆0 = 𝑉 𝐺𝑆3 ⇒ 𝑉 𝐺𝐷2 =0⇒ 𝑉 𝐷𝑆2 = 𝑉 𝐺𝑆2 = 𝑉 𝐺𝑆 The minimum allowable voltage at node P is equal to 𝑉 𝑃 = 𝑉 𝐺𝑆2 + 𝑉 𝐷𝑆3 = 𝑉 𝐺𝑆 + 𝑉 𝐺𝑆0 − 𝑉 𝑇𝐻 　　　　　　　 = 𝑉 𝐺𝑆0 − 𝑉 𝑇𝐻 + 𝑉 𝐺𝑆 − 𝑉 𝑇𝐻 + 𝑉 𝑇𝐻 　　　　　　　　 (Assume the same VTH in M0-M3)
The voltage of VN 𝑉 𝑁 = 𝑉 𝐺𝑆2 + 𝑉 𝐺𝑆3 = 𝑉 𝐺𝑆0 + 𝑉 𝐺𝑆
For M2 to be in saturation region, Vb can be chosen
as low as 𝑉 𝑏 = 𝑉 𝐺𝑆3 + 𝑉 𝐷𝑆2 = 𝑉 𝐺𝑆3 + 𝑉 𝐺𝑆 − 𝑉 𝑇𝐻 𝑉 𝑝 = 𝑉 𝑏 − 𝑉 𝑇𝐻 = 𝑉 𝐺𝑆3 + 𝑉 𝐺𝑆 −2 𝑉 𝑇𝐻
Vp in Fig.5.11(a) is lower than that in Fig.5.11(b) by VTH. But the output current does not accurately track IREF )
(b)
(a)
Chung-Yu (Peter) Wu 2016

5. Chapter 5 Passive and Active Current Mirrors
5.2 Cascode Current Mirror – Low-Voltage Cascode Current Mirror
To eliminate the accuracy-headroom trade-off.
For M2 to be saturated 　　 𝑉 𝑏 − 𝑉 𝐴 − 𝑉 𝑇𝐻2 ≤ 𝑉 𝑋 = 𝑉 𝐺𝑆1 − 𝑉 𝐴 　　⇒ 𝑉 𝑏 − 𝑉 𝑇𝐻2 ≤ 𝑉 𝐺𝑆1
For M1 to be saturated 　　 𝑉 𝐺𝑆1 − 𝑉 𝑇𝐻1 ≤ 𝑉 𝐴 (= 𝑉 𝑏 − 𝑉 𝐺𝑆2 )
Thus 　　 𝑉 𝐺𝑆2 + 𝑉 𝐺𝑆1 − 𝑉 𝑇𝐻1 ≤ 𝑉 𝑏 ≤ 𝑉 𝐺𝑆1 + 𝑉 𝑇𝐻2
A solution exist if 𝑉 𝐺𝑆2 + 𝑉 𝐺𝑆1 − 𝑉 𝑇𝐻1 ≤ 𝑉 𝐺𝑆1 + 𝑉 𝑇𝐻2 ⇒ 𝑉 𝐺𝑆2 − 𝑉 𝑇𝐻2 ≤ 𝑉 𝑇𝐻1 　　　　　　　 Size M2 such that the overdrive voltage is smaller than 𝑉 𝑇𝐻1
Through proper ratio : 　　 𝑉 𝐺𝑆2 = 𝑉 𝐺𝑆4 　　If 𝑉 𝑏 = 𝑉 𝐺𝑆2 + 𝑉 𝐺𝑆1 − 𝑉 𝑇𝐻1 = 𝑉 𝐺𝑆4 + 𝑉 𝐺𝑆3 − 𝑉 𝑇𝐻3 , 　　⇒ 𝑉 𝐴 = 𝑉 𝐺𝑆1 − 𝑉 𝑇𝐻1 　　⇒minumum 𝑉 𝑃 = 𝑉 𝑏 − 𝑉 𝑇𝐻4 = 𝑉 𝐺𝑆4 − 𝑉 𝑇𝐻4 +( 𝑉 𝐺𝑆3 − 𝑉 𝑇𝐻3 ) 　　　Headroom  and 𝑉 𝐴 = 𝑉 𝐵 = 𝑉 𝑏 − 𝑉 𝐺𝑆2 = 𝑉 𝐺𝑆1 − 𝑉 𝑇𝐻1 = 𝑉 𝐺𝑆3 − 𝑉 𝑇𝐻3 ⇒ 𝐼 𝑜𝑢𝑡 = 𝐼 𝑅𝐸𝐹
Chung-Yu (Peter) Wu 2016

6. Chapter 5 Passive and Active Current Mirrors
5.2 Cascode Current Mirror – Low-Voltage Cascode Current Mirror
Generation of biased voltage Vb
Through proper sizing on M5 and M2, 　 𝑉 𝐺𝑆5 ≈ 𝑉 𝐺𝑆2 　 𝑉 𝐷𝑆6 = 𝑉 𝐺𝑆6 − 𝐼 1 𝑅 𝑏 = 𝑉 𝐷𝑆1 = 𝑉 𝐴 = 𝑉 𝐺𝑆1 − 𝑉 𝑇𝐻1 Through proper sizing on M6 and M1, 　 𝑉 𝐺𝑆6 ≈ 𝑉 𝐺𝑆1 　⇒ 𝐼 1 𝑅 𝑏 = 𝑉 𝑇𝐻6 = 𝑉 𝑇𝐻1 　　I1 and Rb can be designed.
Some inaccuracy arises because M5 does not suffer
from body effect whereas M2 does. Similarly, M1 versus M6 .
I1Rb is not well controlled because of the variations of Rb.
The diode connected transistor M7 has a large W/L such that 　　 𝑉 𝐺𝑆7 ≈ 𝑉 𝑇𝐻7 　　 𝑉 𝐷𝑆6 ≈ 𝑉 𝐺𝑆6 − 𝑉 𝑇𝐻7 　　 𝑉 𝑏 = 𝑉 𝐺𝑆5 + 𝑉 𝐺𝑆6 − 𝑉 𝑇𝐻7
This circuit suffers from similar errors due to body effect
𝑉 𝐺𝑆7 ≈ 𝑉 𝑇𝐻7 is well controlled.
Chung-Yu (Peter) Wu 2016

7. Chapter 5 Passive and Active Current Mirrors
5.2 Cascode Current Mirror –
Wide-Swing Cascode using A Source Follower Level Shifter
Shift the gate voltage of M3 down with respect to VN by interposing a source follower.
Proper sizing MS 
𝑉 𝐺𝑆𝑠 = 𝑉 𝑇𝐻3 = 𝑉 𝑇𝐻𝑠
𝑉 𝑁 ′ ≈ 𝑉 𝑁 − 𝑉 𝑇𝐻3
𝑉 𝐵 = 𝑉 𝐺𝑆1 + 𝑉 𝐺𝑆0 − 𝑉 𝑇𝐻3 − 𝑉 𝐺𝑆3
　= 𝑉 𝐺𝑆1 − 𝑉 𝑇𝐻3 (∵ 𝑉 𝐺𝑆0 ≈ 𝑉 𝐺𝑆3 𝑏𝑦 𝑠𝑖𝑧𝑖𝑛𝑔)
Ms is biased at a very low current density,
𝑉 𝐺𝑆𝑠 − 𝑉 𝑇𝐻𝑠 = 2𝐼 𝜇 𝑛 𝐶 𝑜𝑥 𝑊 𝐿 ≈0
𝑉 𝐺𝑆𝑠 ≈ 𝑉 𝑇𝐻𝑠 = 𝑉 𝑇𝐻3
M2 is at the edge of the saturation region.
Substantial current mismatch is introduced for
𝑉 𝐷𝑆2 ≠ 𝑉 𝐷𝑆1
If the body effect of M0, MS, and M3 is considered, it is difficult to guarantee that M2 operates in saturation.
Chung-Yu (Peter) Wu 2016

8. Chapter 5 Passive and Active Current Mirrors
5.3 Active Current Mirror Loads
Current mirror can also process signals as active loads
𝑀 1 ≡ 𝑀 2 , the signal voltage across gate and source of M1 or M2 is 𝑉 𝑖𝑛 2 𝑔 𝑚1 = 𝑔 𝑚2 　　
The output impedance looking into the drain of M2 is
　　　　　　　　　　　　　　　　　　　　　　　　　　( =0, no body effect)
Thus,
𝐴 𝑣 = 𝐺 𝑚 𝑅 𝑜𝑢𝑡 　 𝐺 𝑚 = 𝐼 𝑜𝑢𝑡 𝑉 𝑖𝑛 = 𝑔 𝑚1 𝑉 𝑖𝑛 2 𝑉 𝑖𝑛 = 𝑔 𝑚1 2
1+ 𝑔 𝑚2 𝑟 𝑜 𝑔 𝑚1 + 𝑟 𝑜2 =2 𝑟 𝑜 𝑔 𝑚1 ≈2 𝑟 𝑜2
𝑅 𝑜𝑢𝑡 ≈ 2 𝑟 𝑜2 𝑟 𝑜4 ⇒ 𝐴 𝑣 ≈ 𝑔 𝑚 𝑟 𝑜2 𝑟 𝑜4 　If 𝑟 𝑜4 →∞⇒ 𝐴 𝑣 ≈ 𝑔 𝑚1 𝑟 𝑜2
Chung-Yu (Peter) Wu 2016

9. Chapter 5 Passive and Active Current Mirrors
5.3 Active Current Mirror Loads
An Alternative Solution (  = 0 )
𝑉 𝑜𝑢𝑡 𝑉 𝑖𝑛 = 𝑉 𝑜𝑢𝑡 𝑉 𝑃 𝑉 𝑃 𝑉 𝑖𝑛 　 𝑉 𝑃 𝑉 𝑖𝑛 = 𝑅 𝑒𝑞 𝑅 𝑒𝑞 + 1 𝑔 𝑚1
𝑅 𝑒𝑞 ≈ 1 𝑔 𝑚2 + 𝑟 𝑜4 𝑔 𝑚2 𝑟 𝑜2 = 1 𝑔 𝑚 𝑟 𝑜4 𝑟 𝑜2
𝑉 𝑃 𝑉 𝑖𝑛 = 1 𝑔 𝑚 𝑟 𝑜4 𝑟 𝑜 𝑔 𝑚 𝑔 𝑚 𝑟 𝑜4 𝑟 𝑜2 = 1+ 𝑟 𝑜4 𝑟 𝑜 𝑟 𝑜4 𝑟 𝑜2
𝐼𝑓 𝑟 𝑜4 ≪ 𝑟 𝑜2 ,　 𝑉 𝑃 𝑉 𝑖𝑛 ≈ 1 2
𝑉 𝑜𝑢𝑡 𝑉 𝑖𝑛 = 1+ 𝑟 𝑜4 𝑟 𝑜 𝑟 𝑜4 𝑟 𝑜2 ∙ 𝑔 𝑚2 𝑟 𝑜 𝑟 𝑜2 𝑟 𝑜4 = 𝑔 𝑚2 𝑟 𝑜2 𝑟 𝑜4 2 𝑟 𝑜2 + 𝑟 𝑜4 = 𝑔 𝑚 𝑟 𝑜2 𝑟 𝑜4
Chung-Yu (Peter) Wu 2016

10. Chapter 5 Passive and Active Current Mirrors
5.3 Active Current Mirror Loads – Differential to Single-Ended Amplifier
Current combination utilizing current mirror.
Chung-Yu (Peter) Wu 2016

11. Chapter 5 Passive and Active Current Mirrors
5.3 Active Current Mirror Loads
5.3.1 Large-Signal Analysis
If Vin1 is much more negative than Vin2 , M1 is off and so are M3 and M4. Both M2 and M5 operate in deep triode region.　Vout=0
For a small difference between Vin1 and Vin2 , M1 – M4 are saturated, providing a high gain.
The minimum input common-mode voltage level of Vin,CM = VGS1,2+VDS5,min. VDS5,min : minimum VDS5 such that M5 SAT. The maximum value is VDD - |VGS3| - 𝑉 𝑇𝐻2 .
With perfect symmetry, Vout = VF = VDD - |VGS3| . Gate and Drain of M4 are virtually short.
But Vout can vary a lot if device mismatches occur.
Chung-Yu (Peter) Wu 2016

12. Chapter 5 Passive and Active Current Mirrors
5.3 Active Current Mirror Loads
5.3.2 Small-Signal Analysis – First approach
𝑅 𝑜2 = 𝑟 𝑜 𝑔 𝑚2 𝑟 𝑜 𝑔 𝑚1 ≈2 𝑟 𝑜2
For 𝑔 𝑚1 = 𝑔 𝑚2 = 𝑔 𝑚 　　 𝑔 𝑚2 𝑟 𝑜2 ≫1
⇒ 𝑅 𝑜2 ≅2 𝑟 𝑜2
𝑖 𝑥 =𝑖+𝑖+ 𝑣 𝑥 𝑟 𝑜4 =2𝑖+ 𝑣 𝑥 𝑟 𝑜4 =2 𝑣 𝑥 𝑅 𝑜2 + 𝑣 𝑥 𝑟 𝑜4
𝑖 𝑥 =2 𝑣 𝑥 𝑅 𝑜2 + 𝑣 𝑥 𝑟 𝑜4
𝑅 𝑜 ≡ 𝑣 𝑥 𝑖 𝑥 = 𝑟 𝑜2 𝑟 𝑜4
Chung-Yu (Peter) Wu 2016

13. Chapter 5 Passive and Active Current Mirrors
5.3 Active Current Mirror Loads
5.3.2 Small-Signal Analysis – First approach
M2 ground drain M1 small drain impedance  P is virtually grounded
𝐼 𝑜𝑢𝑡 = 𝐼 𝑑4 − 𝐼 𝑑2 = 𝐼 𝑑1 − 𝐼 𝑑2 = 𝑔 𝑚1 𝑉 𝑖𝑛 2 − 𝑔 𝑚2 − 𝑉 𝑖𝑛 2 　 = 𝑔 𝑚 1,2 𝑉 𝑖𝑛 　　　 𝑔 𝑚1 = 𝑔 𝑚2 = 𝑔 𝑚 1,2 𝐺 𝑚 = 𝑔 𝑚 1,2 𝐴 𝑣 = 𝐺 𝑚 𝑅 𝑜𝑢𝑡 = 𝑔 𝑚 1,2 ( 𝑟 𝑜2 𝑟 𝑜4 )
(a)
(b)
Vout from in at M1  positive
Vout from in at M2  negative
Chung-Yu (Peter) Wu 2016

14. Chapter 5 Passive and Active Current Mirrors
5.3 Active Current Mirror Loads
5.3.2 Small-Signal Analysis – Second approach
𝑉 𝑒𝑞 = 𝑔 𝑚 1,2 𝑟 𝑜 1,2 𝑉 𝑖𝑛 𝑅 𝑒𝑞 =2 𝑟 𝑜 1,2
𝐼 𝑋1 = 𝑉 𝑜𝑢𝑡 − 𝑔 𝑚 1,2 𝑟 𝑜 1,2 𝑉 𝑖𝑛 2 𝑟 𝑜 1, 𝑔 𝑚3 𝑟 𝑜3
The current flowing through 1 𝑔 𝑚3 is mirrored to the drain of M4.
𝐼 𝑋1 + 𝐼 𝑋1 𝑟 𝑜3 𝑟 𝑜 𝑔 𝑚3 =− 𝑉 𝑜𝑢𝑡 𝑟 𝑜4
2 𝑟 𝑜 1,2 ≫ 1 𝑔 𝑚 3,4 𝑟 𝑜 3,4 and 𝑟 𝑜3 ≫ 1 𝑔 𝑚3
⇒ 𝑉 𝑜𝑢𝑡 𝑉 𝑖𝑛 = 𝑔 𝑚 1,2 ( 𝑟 𝑜 1,2 𝑟 𝑜 3,4 )
(b)
(a)
Chung-Yu (Peter) Wu 2016

15. Chapter 5 Passive and Active Current Mirrors
5.3 Active Current Mirror Loads
5.3.3 Common-Mode Properties
The active-loaded MOS differential amplifier has a low common mode gain and a high CMRR.
Chung-Yu (Peter) Wu 2016

16. Chapter 5 Passive and Active Current Mirrors
5.3 Active Current Mirror Loads
5.3.3 Common-Mode Properties -Under mismatched input transistors
𝑔 𝑚 1 is not equal to 𝑔 𝑚 2 :
Chung-Yu (Peter) Wu 2016