2. Parity system? VME Crate Xp, Xm muxed Xin Yin +Xp +Xm +Yp +Ym Xin Yin
XY OUT Xo Yo
Parity system? Xp Yp Xm Ym RF
Module
Yp, Ym muxed
ADC In
Control signals
VMIC
3115 IF
S/H
RF Module
Xp, Yp, Xm, Ym inputs are from wires on BPM filtered at 1497 MHz in front end. RF module can drive one port at a time with 1497 MHz at various amplitudes
Outputs are time domain multiplexed Xp, Xm, . . .Yp, Ym signals at 45 MHz.
Control signals 9-pin D connector control oscillator and switch clock.
IF card
Xin and Yin -- time domain multiplexed 45 MHz signal
XY Out – time domain multiplexed 0V to 5V, Xp, Yp, Xm, Ym, Xp, Yp Clocked with Data_Clock which is nominally there for short bursts following a beam sync. This data clock is not used by the S/H cards.
Xo, Yo Time domain multiplexed 0 to 5 V Xp, Xm, Xp, Xm And Yp, Ym, Yp, Ym
S/H card
Xin, Ym Time domain multiplexed 0 to 5 V Xp, Xm, Xp, Xm And Yp, Ym, Yp, Ym
Demultiplexed with Sample and held and continuously updated at the switch clock rate.
The data is frozen, but still valid, for one switch clock every beam sync.
+Xp, +Xm, +Yp, and +Ym are the outputs of the sample and hold card which are filtered at something like 32 kHz for a linac style crates. There is also a copy of the same signals with negative polarity.
All signals are single ended grounded (to the beam line for RF and to the AC power bus for the VME Crate) signals