1. Using FPro SoC with customized hardware cores
ECE 448: Lab 4
Using FPro SoC with customized hardware cores
(cont)

2. Agenda for today Part 1: Basic MIMO I/O Core Construction (Timer Core)
Part 2: Lab 4 Exercise 2

3. Basic MIMO I/O Core Construction
Part 1
Basic MIMO I/O Core Construction
(Timer Core)
ECE 448 – FPGA and ASIC Design with VHDL

4. Basic MIMO I/O Core Construction
Design the custom digital circuit
Determine the I/O register map for the slot interface
Derive the wrapping circuit
Develop the hardware
Develop the software driver
Develop an application based on the driver

5. Timer Core 48-bit counter value
The processor interacts with the counter as follows:
retrieve (i.e., read) the counter value.
set or reset (i.e., write) a “go” signal to resume or pause the counting.
generate (i.e., write) a “clear” pulse to clear the counter to 0.

6. Block Diagram

7. Basic MIMO I/O Core Construction
Design the custom digital circuit
Determine the I/O register map for the slot interface
Derive the wrapping circuit
Develop the hardware
Develop the software driver
Develop an application based on the driver

8. Interface

9. MIMO Slot Interface Specification
A slot is a 32-word (25-word) memory module. The slot interface is defined as follows:
addr (bus to core). A 5-bit address signal used to identify the 32-bit destination I/O register within the core.
rd_data (core to bus). A 32-bit signal carrying the read data.
wr_data (bus to core). A 32-bit signal carrying the write data.
read (bus to core). A 1-bit control signal activated with the read operation.
write (bus to core). A 1-bit control signal to enable the register write.
cs (bus to core). A 1-bit enable (i.e., “chip select”) signal to select and activate the core.

10. IO Register Map of Timer Core
offset 0 (lower word of the counter) – bits 31 to 0: 32 LSBs of the counter
offset 1 (upper word of the counter) – bits 15 to 0: 16 MSBs of the counter
offset 2 (control register)
–bit 0: the go signal of the counter
–bit 1: the clear signal of the counter

11. IO Register Map of Timer Corecs
write
read
addr(1:0)
wr_data(1:0)
Operation 1 00 xx
Read lower word 01
Read upper word 10 x1
Set “go” signal x0
Reset “go” signal 1x
Set “clear” signal

12. Basic MIMO I/O Core Construction
Design the custom digital circuit
Determine the I/O register map for the slot interface
Derive the wrapping circuit
Develop the hardware
Develop the software driver
Develop an application based on the driver

13. Wrapping Circuit cs write read addr(1:0) wr_data(1:0) Operation 1 0000 xx
Read lower word 01
Read upper word 10 x1
Set “go” signal x0
Reset “go” signal 1x
Set “clear” signal

14. Basic MIMO I/O Core Construction
Design the custom digital circuit
Determine the I/O register map for the slot interface
Derive the wrapping circuit
Develop the hardware
Develop the software driver
Develop an application based on the driver

15. Existing slot for Timer core in
chu_io_map.vhd

16. Instantiating the Timer core in
mmio_sys_sampler_basys3.vhd

17. Instantiating User core in
mmio_sys_sampler_basys3.vhd

18. Basic MIMO I/O Core Construction
Design the custom digital circuit
Determine the I/O register map for the slot interface
Derive the wrapping circuit
Develop the hardware
Develop the software driver
Develop an application based on the driver

19. I/O Macros in chu_io_rw.h

20. Slot and constant definitions in chu_io_map.h

21. TimerCore class definition
in timer_core.h

22. TimerCore class implementation
in timer_core.cpp
TimerCore::TimerCore(uint32_t core_base_addr) {
base_addr = core_base_addr;
ctrl = 0x01;
clear();
io_write(base_addr, CTRL_REG, ctrl); // enable the timer }
TimerCore::~TimerCore() {
void TimerCore::pause() {
// reset enable bit to 0
ctrl = ctrl & ~GO_FIELD;
io_write(base_addr, CTRL_REG, ctrl);
void TimerCore::go() {
// set enable bit to 1
ctrl = ctrl | GO_FIELD;

23. TimerCore class implementation
in timer_core.cpp
void TimerCore::clear() {
uint32_t wdata;
// write clear_bit to generate a 1-clock pulse
// clear bit does not affect ctrl
wdata = ctrl | CLR_FIELD;
io_write(base_addr, CTRL_REG, wdata); }
uint64_t TimerCore::read_tick() {
uint64_t upper, lower;
lower = (uint64_t) io_read(base_addr, COUNTER_LOWER_REG);
upper = (uint64_t) io_read(base_addr, COUNTER_UPPER_REG);
return ((upper << 32) | lower);

24. Basic MIMO I/O Core Construction
Design the custom digital circuit
Determine the I/O register map for the slot interface
Derive the wrapping circuit
Develop the hardware
Develop the software driver
Develop an application based on the driver

25. Application Code #include "chu_io_map.h" #include "timer_core.h"
TimerCore timer((get_slot_addr(BRIDGE_BASE, S0_SYS_TIMER)));
int main(){
timer.clear();
timer.go();
timer.pause();
uint64_t ticks = timer.read_tick(); }

26. Part 2
Lab 4 Exercise 2
ECE 448 – FPGA and ASIC Design with VHDL