1. 1 The LPC1768 Architecture (with focus on Cortex-M3)

2. 2 LPC 1768  LPC 1768 is an ARM Cortex-M3 based microcontroller for embedded applications by NXP company  3-stage pipeline, Harvard architecture  Up to 100 Mhz Clock, 12Mhz crystal frequency  On-chip memory: 512KB flash and 64KB RAM  USB  2 CAN interface  2 serial port  Resources from Keil.com www.keil.com/dd/chip/4868.htmwww.keil.com/dd/chip/4868.htm

3. 3 LPC 1768 Memory Map (4 GB)

4. 4 Today Agenda LPC1768 Overview GPIO (user manual: chapter 9) System Tick Timer (user manual: chapter 23)

5. 5 LPC 1768 GPIO (ch9)  On Reset, the pin connect block configures all peripheral pins to be general purpose I/O input pins.  The GPIO pins are controlled by five registers, as shown:  FIOxDIRy Fast GPIO Port Direction control register 0: Controlled pin is input; 1: Controlled pin is output  FIOxMASKy Fast Mask register for port. 0: Controlled pion is not masked; 1: controlled pin is masked  FIOxPINy Fast Port pin value register using FIOMASK Provides the value of port pins.  FIOxSET Fast Port Output Set register using FIOMASK 0: Controlled pin output is unchanged; 1: Controlled pin output is ‘1’  FIOxCLR Fast Port Output Clear Register 0: Controlled pin output is unchanged; 1: Controlled pin output is ‘0’

6. 6 LPC 1768 GPIO  GPIO Interrupt register map  IntEnR GPIO Interrupt Enable for Rising Edge  IntEnF GPIO interrupt enable for falling edge  IntStatR GPIO interrupt status for rising edge  IntStatF GPIO interrupt status for falling edge  IntClr GPIO Interrupt Clear  IntStatus GPIO overall Interrupt status

7. 7 LPC 1768 System Tick Timer (ch23)  The System Tick timer is an integral part of the Cortex-M3. the System tick timer is intended to generate a fixed 10 ms (it can be configured) interrupt for use by an RTOS.  The system tick timer is a 24-bit timer that counts down to zero and generates an interrupt.  The system tick timer may be clocked either from the CPU clock CCLK or from the external pin STCLK.

8. 8 LPC 1768 System Tick Timer

9. 9 System Tick Timer Registers

10. 10 Control and Status Registers

11. 11 System Timer Reload Registers

12. 12 ARM CMSIS  CMSIS is a vendor-independent hardware abstraction layer for the Cortex-M processor series. The CMSIS enables consistent and simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning curve for new microcontroller developers and reducing the time to market for new devices.Cortex-M processor  ARM CMSIS Source and download ARM CMSIS Source and download  MDK ARM Primer, MDK ARM Primer,

13. 13 LPC 1768 System Tick Timer (ch23)  In MDK5.10 which supports CMSIS 3.0, simply call the function SysTick_Config(SystemCoreClock/100);  However, in ECE 362 Lab, you are NOT allowed to use CMSIS library.  The period of system tick interrupt time is 1000/100 = 10 ms. typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; #define SysTick_BASE (0xE000E000UL+ 0x0010UL) /*!< SysTick Base Address */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */

14. 14 LPC 1768 System Tick Timer (ch23)  typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; #define SysTick_BASE (0xE000E000UL+ 0x0010UL) /*!< SysTick Base Address */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ SysTick_Init(uint32_t ticks) { SysTick->LOAD = ticks & 0xFFFFFF - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, 1); /* set Priority for Systick Interrupt */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = 0x00000007/* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ }

15. 15 LPC 1768 NVIC (6)  LPC 1768: Nested Vectored Interrupt Controller  NVIC supports 35 vectored interrupts.  32 programmable interrupt priority levels, (0 highest)  Relocateable vector table  Non-Maskable Interrupt (NMI)  Exceptions and hardware interrupts  Interrupts: enable/disable/ active/pending,

16. 16 LPC 1768 NVIC Interests:

17. 17 LPC 1768 PCONP (page 62 chapter 4)  The PCONP register allows turning off selected peripheral functions for the purpose of saving power. This is accomplished by gating off the clock source to the specified peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer, the Pin Connect block, and the System Control block).  Some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Information on peripheral specific power saving features may be found in the chapter describing that peripheral.  If a peripheral control bit is 1, that peripheral is enabled. If a peripheral control bit is 0, that peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the I2C1 interface is enabled. If bit 19 is 0, the I2C1 interface is disabled.  For example, configure PCONP to use ADC LPC_SC->PCONP |= 1<<12;

18. 18 LPC 1768 pin configuration (ch 7 &8)  I/O pins on the LPC17xx are 5V tolerant and have input hysteresis unless indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5V tolerant. In addition, when pins are selected to be A to D converter inputs, they are no longer 5V tolerant and must be limited to the voltage at the ADC positive reference pin (VREFP).  One pin may be shared with multiple functions, for example, P0.25 – GPIO (I/O), AD0 (channel 0 input), I2SRX_SDA (I2S I/O), TXD3 (O)  Can be configured using registers PINSELn  Each pin can be configured as pull-down, pull-down, repeater mode, neither pull-down/pull-down, etc. using registers PINMODELn  ARMwizard: a free app to setup ARM registers from mbed http://mbed.org/users/alexan_e/notebook/armwizard-v30-freeware-app- for-lpc2xxx-17xx-13xx-1/