1. Random-Access Memory (RAM)
Princess Sumaya University
Digital Logic Design
Random-Access Memory (RAM)
Data Storage (Volatile)
Locations (Address)
Byte or Word
Data input
Memory unit
16 x 8
Address
Read
Write
Data output
Dr. Bassam Kahhaleh

2. Random-Access Memory (RAM)
Princess Sumaya University
Digital Logic Design
Random-Access Memory (RAM)
Data Storage (Volatile)
Locations (Address)
Byte or Word
m Data input
Memory unit
2k x m
k Address
10 Address lines  1024 locations = 1 K
Read
Write
m Data output
Dr. Bassam Kahhaleh

3. Memory Decoding Memory Array Input Data I1 AddressLines I0 1BC
Input Data
Output Data 1 2 3
2 x 4 Decoder I1 I0 E
AddressLines
Memory Enable
Read/Write

4. Memory Decoding
Memory Cell
Select BC
Input
Output
Read/Write

5. Programmable Configurations
Read Only Memory (ROM) –
a fixed array of AND gates and a programmable array of OR gates
Programmable Array Logic (PAL)Ò –
a programmable array of AND gates feeding a fixed array of OR gates.
Programmable Logic Array (PLA) –
a programmable array of AND gates feeding a programmable array of OR gates.
Complex Programmable Logic Device (CPLD) /Field- Programmable Gate Array (FPGA) –
complex enough to be called “architectures”

6. ROM, PAL and PLA Configurations
Fixed
Programmable
Programmable
Inputs
AND array
Outputs
Connections
OR array
(decoder)
(a) Programmable read-only memory (PROM)
Programmable
Inputs
Programmable
Fixed
Outputs
Connections
AND array
OR array
(b) Programmable array logic (PAL) device
Programmable
Programmable
Programmable
Programmable
Inputs
Outputs
Connections
AND array
Connections
OR array
(c) Programmable logic array (PLA) device

7. Read Only Memory
Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have:
N input lines,
M output lines, and
2N decoded minterms.
Fixed AND array with 2N outputs implementing all N-literal minterms.
Programmable OR Array with M outputs lines to form up to M sum of minterm expressions.
A program for a ROM or PROM is simply a multiple-output truth table
If a 1 entry, a connection is made to the corresponding minterm for the corresponding output
If a 0, no connection is made

8. Read Only Memory Example
Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)
The fixed "AND" array is a “decoder” with 3 inputs and 8 outputs implementing minterms.
The programmable "OR“ array uses a single line to represent all inputs to an OR gate. An “X” in the array corresponds to attaching the minterm to the OR
Read Example: For input (A2,A1,A0) = 011, output is (F3,F2,F1,F0 ) = 0011.
What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)? D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 A B C F0 F1 F2 F3 X
F3 = D7 + D5 + D2 = A2 A0 + A2’ A1 A0’
F2 = D7 + D0 = A2 A1 A0 + A2’ A1’ A0’
F1 = D4 + D1 = A1 A1’ A0’ + A2’ A1’ A0
F0 = D7 + D5 + D1 = A2 A0 + A1’ A0

9. Read-Only Memory (ROM)
2k x m
k Address
Memory Enable
m Data output

10. Read-Only Memory (ROM)
Conventional Symbol
Array Logic Symbol

11. Read-Only Memory (ROM)
8 x 4 ROM
3 x 8 Decoder 1 2 I2
AddressLines 3 I1 4 I0 5
Memory Enable 6 E 7
Output Data

12. Read-Only Memory (ROM)
8 x 4 ROM
3 x 8 Decoder
Address
Data 1 2 A2 I2 3 A1 I1 4 A0 I0 5 6 1 E 7 D3 D2 D1 D0

13. Types of ROMs Mask Programmed ROM Programmable Read-Only Memory (PROM)
Programmed during manufacturing
Programmable Read-Only Memory (PROM)
Blow out fuses to produce ‘0’
Erasable Programmable ROM (EPROM)
Erase all data by Ultra Violet exposure
Electrically Erasable PROM (EEPROM)
Erase the required data using an electrical signal

14. Programmable Logic Device (PLD)
Boolean Functions:
Sums-of-Products
AND-plane followed by OR-plane

15. Programmable Logic Device (PLD)
PROM
PAL
PLA
Fixed
AND array
(Decoder)
Programmable
OR array
Inputs
Outputs
Programmable
AND array
Fixed
OR array
Inputs
Outputs
Programmable
AND array
OR array
Inputs
Outputs

16. Programmable Array Logic (PAL)
Example
w(A,B,C,D) = ∑(2,12,13)
x(A,B,C,D) = ∑(7,8,9,10,11,12,13,14,15)
y(A,B,C,D) = ∑(0,2,3,4,5,6,7,8,10,11,15)
z(A,B,C,D) = ∑(1,2,8,12,13)
Simplify:
w = ABC’ + A’B’CD’
x = A + BCD
y = A’B + CD + B’D’
z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D
= w + AC’D’ + A’B’C’D w A x B y C z D

17. Programmable Logic Array (PLA)
Example:
F1 = AB’ + AC + A’BC’
F2 = (AC + BC)’

18. Sequential Programmable Logic Device
Basic Macrocell Logic

19. Programmable Array Logic (PAL)
The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs.
Disadvantage
ROM guaranteed to implement any M functions of N inputs. PAL may have too few inputs to the OR gates.
Advantages
For given internal complexity, a PAL can have larger N and M
Some PALs have outputs that can be complemented, adding POS functions
No multilevel circuit implementations in ROM (without external connections from output to input). PAL has outputs from OR terms as internal inputs to all AND terms, making implementation of multi-level circuits easier.

20. Programmable Array Logic Example9 1 2 3 4 5 6 7 8
AND gates inputs
Product
term 10 11 12 F I = C B A
4 = D X
4-input, 3-output PAL with fixed, 3-input OR terms
What are the equations for F1 through F4?
F1 = C’ + A’B’
F2 = A’BC’ + AC + AB’
F3 = AD + BD + F1
F4 = AB + CD + F1’
F3 = AD + BD + F1 = AD + BD + A’B+ C’ = AD + BD + A’B’ + C’
F4 = AB + CD + F1’ = AB + CD + (A’B’ + C’)’ = AB + CD + AC + BC

21. Programmable Logic Array (PLA)
Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs.
Advantages
A PLA can have large N and M permitting implementation of equations that are impractical for a ROM (because of the number of inputs, N, required 
A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL ORs
Some PLAs have outputs that can be complemented, adding POS functions
Disadvantage
Often, the product term count limits the application of a PLA. Two-level multiple-output optimization reduces the number of product terms in an implementation, helping to fit it into a PLA.

22. Programmable Logic Array Example
Fuse intact
Fuse blown 1 F 2 X A B C 3 4
A B
A C
B C
What are the equations for F1 and F2?
Could the PLA implement the functions without the XOR gates?
F1 = AB +BC + AC
F2 = (AB + A’B’)’ = (A’ + B’) (A + B) = A’B + AB’
No. If only SOP functions used, requires at least 5 AND gates.
3-input, 3-output PLA with 4 product terms