1. Implementing Combinational and Sequential Logic in VHDL
ECE 448
Lab 2
Implementing Combinational and Sequential Logic in VHDL
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University

2. Agenda for today Part 1: Introduction to Lab 2
Implementing Combinational and Sequential
Logic in VHDL
Part 2: ModelSim Demo
Part 3: Lab 2 Exercise
Part 4: Lab 1 Demos and Q&A

3. Part 1 Introduction to Lab 2
ECE 448 – FPGA and ASIC Design with VHDL

4. Multiplication by Squaring
Task 1
Multiplication by Squaring

5. Multiplication by Squaring
(a+x)2 - (a-x)2
a  x = 4

6. Block Diagram
a+x
(a+x)2
|a-x|
(a-x)2

7. Calculating |a-x| cout 0 a3 a2 a1 a0 0 x3 x2 x1 x0 0 a3 a2 a1 a0+1 +1
Sign of difference a-x = cout xor 1 = cout
a-x >= 0 iff cout = 1
a-x < 0 iff cout = 0
|a-x| will always fit on 4 bits
because it is always smaller than or equal to max{a,x}

8. Deliverables 1. RTL VHDL code of the Multiplication by Squaring unit.
2. Advanced testbench for the Multiplication by Squaring unit.
3. ModelSim waveforms obtained by applying your testbench (in the PDF format).

9. Multiplication by Squaring
Bonus Task 1
Multiplication by Squaring
using Dual-Port ROM

10. Task
Modify the block diagram of the Multiplication by Squaring unit, assuming the use of a single dual-port ROM instead of two single-port ROMs.
Implement the modified circuit in RTL VHDL and verify its functionality using the testbench developed in Part 1.

11. Deliverables
Block diagram of your modified Multiplication by Squaring unit.
RTL VHDL code of the modified Multiplication by Squaring unit.
ModelSim waveforms obtained by applying your testbench (in the PDF format).

12. Shift/subtract sequential restoring divider for unsigned integers
Task 2
Shift/subtract sequential restoring divider for unsigned integers

13. Naming Conventions z Dividend z2k-1z2k-2 . . . z2 z1 z0
d Divisor dk-1dk d1 d0
q Quotient qk-1qk q1 q0
r Remainder rk-1rk r1 r0
q = 𝑧/𝑑
r = z – d ∙ q
0 ≤ r < d

14. Block Diagram

15. Notation

16. Operation 117/10
s(0)
2s(0) d 1
0101 1
10100
01111
01000
00111
q3=1
q3=1
z = = 117
s(1)
2s(1) d 1
d = = 10
q2=0
d = 01012
s(2)
2s(2) d 1
q = = 11
q1=1
r = = 7
s(3)
2s(3) d 1
q0=1
s(4)

18. Deliverables
1. RTL VHDL code of the Shift/subtract sequential restoring divider
2. Simple testbench for the Shift/subtract sequential restoring divider
3. ModelSim waveforms obtained by applying your testbench (in the PDF format).

19. Shift/subtract sequential restoring divider for signed integers
Bonus Task 2
Shift/subtract sequential restoring divider for signed integers

20. Signed Integer Divisionz d
| z |
| d |
sign(z)
sign(d)
Unsigned
division
sign(r) = sign(z) +
sign(z) = sign(d)
| q |
| r |
sign(q) = -
sign(z)  sign(d) q r

21. Deliverables
Block diagram of your modified Shift/subtract sequential restoring divider for signed integers
RTL VHDL code of the Shift/subtract sequential restoring divider for signed integers
Simple testbench for the Shift/subtract sequential restoring divider for signed integers
ModelSim waveforms obtained by applying your testbench (in the PDF format), showing the correct result of division for at least three different sets of inputs z and d, with z7..4 < d.

22. Comparing Vivado Simulator with ModelSim Intel FPGA
Task 3
Comparing Vivado Simulator
with ModelSim Intel FPGA

23. Be ready to demonstrate using both simulators:
Adding signals to the waveform window.
Including signals from lower levels of hierarchy.
Using all options to run simulation.
Introducing breakpoints and showing the execution of logic before and after a breakpoint in the waveform window.
Measuring time intervals.
Dealing with buses (expanding and viewing all bits of a signal).
Taking a signal and changing radix to decimal, binary and hexadecimal.
Saving timing waveforms in native format of the simulators.
Clearing waveforms.

24. Part 2
ModelSim Demo
ECE 448 – FPGA and ASIC Design with VHDL

25. Part 3
Lab 2 Exercise
ECE 448 – FPGA and ASIC Design with VHDL

26. ALU: Interface

28. ALU: Block Diagram

30. Part 4
Lab 1 Demos and Q&A
ECE 448 – FPGA and ASIC Design with VHDL