1. Verilog HDL Basic Syntax
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2. Four valued logic system in Verilog
0: logic low, false, ground
1: logic high, true, power
unknown
High impedance，tri-state
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3. Identifier Begin with A-Z, a-z or _, and letter/number/$/_ follow
Which is true or false?
_aZ89$ $a908d a9b is987
__ada_7Z_ a*b_net _bus3
Case sensitive
AB and ab are different identifiers
Maximum length: 1023 letters
Key words (reserved words): lowercase
module endmodule begin end
assign initial always
if else case endcase
for forever while repeat
reg wire integer parameter
posedge negedge
input output inout or default
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4. <size>’<base><value>
Constant
Syntax:
<size>’<base><value>
size: size of bits, decimal, default: 32
base: 1. b (binary) o(octonary)
3. d (decimal) 4. h(hexadecimal)
default: decimal
case insensitive
value: any valid number in the selected number base, “_” is available.
Note: When value is larger than size, MSB (Most significant bit) will be truncated to meet the size of bits.
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5. Constant 12 unsized decimal (zero-extended to 32 bits)
’83a unsized hexadecimal (zero-extended to 32 bits)
8’b1100_ bit binary
16’hff bit hexadecimal
3’b1010_ bit number, truncated to 3’b101
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6. Variable type
Net type
Register type
Parameter type
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7. Variable type – Net type
Function
wire, tri
Standard internal connection
supply1
supply0
Power
Ground
wor
Or drive source line
wand
And drive source line
default type: wire
default size: 1 bit
Note: wire type is the most common.
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8. Variable type – Register type
Only be used in always and initial block
Register type
Function
reg
Define unsigned integer
integer
32-bit signed integer
real
Double signed float
time
64-bit unsigned integer, to save time in simulation
reg default size: 1 bit
Note: reg type is the most common in register type.
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9. Variable Declaration Net declaration Register declaration Note:
<net_type> [range][delay] <net_name>[, net_name];
Register declaration
<reg_type> [range] <reg_name>[, reg_name];
Note:
rang: [MSB:LSB]
<>: required
[]: optional
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10. Variable Declaration Example: wire w; // 1 bit net type
wire [15:0] w1, w2; // two 32-bit wire variables, LSB is bit0
wire [0:15] w3, w4; // two 32-bit wire variables, LSB is bit15
reg 1; // 1-bit reg type
reg [3:0] v; // 4-bit reg variable
reg [7:0] m, n; // two 8-bit reg variable
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11. Register Array Syntax:
reg_type [MSB:LSB] <memory_name> [first_addr:last_addr];
[MSB:LSB]: to define the bits of register word
[first_addr:last_addr]: to define the depth of register
Example:
reg [15:0] MEM[0:1023]; // 1K x 16bit register
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12. Register Array - addressing
Register Array Element can be addressed by array index.
mem_name[array_index]
Multidimensional array is not supported in Verilog.
Register Word only.
Bit in Register Word is not supported.
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13. Register Array - addressing
Example
module mems;
reg [8: 1] mem_a [0: 255]; // the definition of mem_a
reg [8: 1] mem_word; // temporary variable: mem_ word
. . .
initial
begin
$displayb( mem_a[5]); // to display the 6th Register Word
mem_word = mem_a[5]; // to save the 6th Register Word
$displayb( mem_word[8]); // to display MSB in the 6th Register Word
end
endmodule
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14. How to choose right data type?
in1
in2 O A B Y
Input port
Must be net type, but can be drived by net/register, (in1, in2 signal in the diagram)
Output port
Can be register type, but only can drive net, (O signal in the diagram)
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15. How to choose right data type?
module DUT (O, in1, in2);
output O;
input in1, in2;
reg in1, in2;
wire O;
or in2)
O=in1+in2;
endmodule
Find errors in the program.
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16. Parameter
Define a variable constant, be often used in the definition of delay, size, etc.
Can define multiple parameters, separated by commas.
Local definition, valid in current module only.
Recommendation:
Upper case in parameter, lower case in variable.
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17. Parameter module mod1( out, in1, in2); . . .
Example
module mod1( out, in1, in2);
. . .
parameter cycle = 20, p1 = 8, setup = cycle/2 – p1;
// rule number 2
wire [p1: 0] w1; // use parameter p1
endmodule
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18. Verilog Operator Priority Operator Type Symbol concatenate & replicate
unary operator
arithmetic operator
logical shift operator
relational operator
equal operator
bitwise operator
logical operator
conditional operator
{} {{}}
！ ~ & | ^
* / %
+ -
<< >>
> < >= <=
= = = = = != != =
&
^ ~^ |
&& || ？:
Priority
high
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low

19. Verilog Operator module bitwise (); reg [3: 0] rega, regb, regc;
reg [3: 0] num;
initial begin
rega = 4'b1001;
regb = 4'b1010; end
#10 num = rega & 0; // num = ?
#20 num = rega & regb; // num = ?
#30 num = rega | regb; // num = ?
end
endmodule
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20. Verilog Operator module logical (); parameter five = 5; reg ans;
reg [3: 0] rega, regb, regc;
initial
begin
rega = 4‘b0011; // logic value“1”
end
initial begin
#10 ans = rega && 0; // ans = ?
#20 ans = rega || 0; // ans = ?
#30 ans = rega && five; // ans = ?
endmodule
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21. Verilog Operator >> logic shift right << logic shift left
module shift ();
reg [9: 0] num, num1;
reg [7: 0] rega, regb;
initial rega = 8'b ;
initial begin
#10 num <= rega << 5 ; // num = 01_1000_0000
#10 regb <= rega << 5 ; // regb = _0000
#20 num <= rega >> 3; // num = 00_0000_0001
#20 regb <= rega >> 3 ; // regb = _0001
#30 num <= 10'b11_1111_0000;
#40 rega <= num << 2; // rega = _0000
#40 num1 <= num << 2; // num1=11_1100_0000
#50 rega <= num >> 2; // rega = 1111_1100
#50 num1 <= num >> 2; // num1=00_1111_1100
end
endmodule
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22. Verilog Operator module concatenation;
{ } concatenate operation
module concatenation;
reg [7: 0] rega, regb, regc, regd;
reg [7: 0] new;
initial begin
rega = 8'b0000_0011;
regb = 8'b0000_0100;
regc = 8'b0001_1000;
regd = 8'b1110_0000;
end
#10 new = {regc[ 4: 3], regd[ 7: 5],
regb[ 2], rega[ 1: 0]};
endmodule
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23. Verilog Operator { {} } replicate operator Syntax: {integer{}}
Function: copy the value that is in the inner {}, the integer indicates the times that copies.
Note: bits must be assigned when concatenate and replicate, or errors will occur.
Wrong Examples:
a[7:0] = {4{ ´b10}};
b[7:0] = {2{ 5}};
c[3:0] = {3´b011, ´b0};
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24. Verilog Operator module replicate (); reg [3: 0] rega;
reg [1: 0] regb, regc;
reg [7: 0] bus;
initial begin
rega = 4’b1001;
regb = 2'b11;
regc = 2'b00;
end
#10 bus <= {4{ regb}}; // bus =
// regb is replicated 4 times.
#20 bus <= { {2{ regb}}, {2{ regc}} };
// bus = regc and regb are each
// replicated, and the resulting vectors
// are concatenated together
#30 bus <= { {4{ rega[1]}}, rega };
// bus = rega is sign-extended
#40 $finish;
endmodule
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25. Verilog Program Structure
Every module begins with a key word “module”, and ends with a key word “endmodule”.
module_name
The description of logic and function implementation is put in the internal of module.
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26. Verilog Program Structure
module gates(a,b,led);
input a,b;
output [5:0] led;
wire [5:0] z;
//Combinational logic style
assign z[5]=a&b; // AND
assign z[4]=~(a&b); // NAND
assign z[3]=a|b; // OR
assign z[2]=~(a|b); // NOR
assign z[1]=a^b; // XOR
assign z[0]=a~^b; // XNOR
assign led=~z;
endmodule
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27. Module Implementation
Implementation name is required.
Positional Mapping
Named Mapping
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28. Module Implementation
module comp (o1, o2, i1, i2);
output o1, o2;
input i1, i2;
. . .
endmodule
module test;
comp c1 (Q, R, J, K); // Positional mapping
comp c2 (.i2(K), .o1(Q), .o2(R), .i1(J)); // Named mapping
Positional Mapping
Named Mapping：
.internal signal（external signal）
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29. Always Statement Function: to do something over and over again.
Level control sensitive events
or B)
Edge trigger control
Clock)
Combination
or posedge Clock)
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30. Always Statement Find error
module HalfAdder(A, B, Sum, Carry); input A, B; output Sum, Carry; or B) begin Sum=A^B; Carry=A&B; end endmodule
Find error
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31. Task 1: Design an adder Find error
module adder (out, a, b, cin); input a, b, cin; output [1:0] out; wire a, b, cin; reg half_sum; wire half_carry; reg [1: 0] out; a or b or cin) begin half_sum = a ^ b ^ cin ; // OK half_carry = a & b | a & !b & cin | !a & b & cin ; out = {half_carry, half_ sum} ; end endmodule
Find error
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32. Obstructive assignment & Non obstructive assignment
Other statement can not be executed when executing this statement, and after execution, variable value changes immediately.
Non obstructive assignment: <=
After execution, variable value can not change immediately. After block execution, variable value will change.
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33. Obstructive assignment & Non obstructive assignment
module swap_vals; reg a, b, clk; initial begin a = 0; b = 1; clk = 0; end always #5 clk = ~clk; posedge clk) begin a <= b; // non obstructive assignment b <= a; // swap the value a and b endmodule
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34. If branch statement if (statement） begin …… end else if (表达式） else
always #20
if (index > 0)
if (rega > regb)
result = rega;
else
result = 0;
if (index == 0)
begin
$display(" Note : Index is zero");
result = regb;
end
$display(" Note : Index is negative");
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35. case branch statement
case <statement> < statement >, < statement >: assign or nop; < statement >, < statement >: assign or nop ; default: assign or nop ;
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36. case branch statement module compute (result, rega, regb, opcode);
input [7: 0] rega, regb;
input [2: 0] opcode;
output [7: 0] result;
reg [7: 0] result;
rega or regb or opcode)
case (opcode)
3'b000 : result = rega + regb;
3'b001 : result = rega - regb;
3'b010 ,
3‘b100 : result = rega / regb;
// two conditions, same operation
default : begin
result = 8'b0000_0000;
$display (" no match");
end
endcase
endmodule
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37. Task 2: Select one signal from two signal
module mux2(out,a,b,sl);
input a,b,sl;
output out;
not u1(nsl,sl);
and u2(sela,a,nsl);
and u3(selb,b,sl);
or u4(out,sela,selb);
endmodule
module mux2(out,a,b,sl);
input a,b,sl;
output out;
reg out;
(sl or a or b)
if (!sl) out = a;
else out = b;
endmodule
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38. Task 3: Seven-segment Decoder
module bin27seg (data_in ,EN ,data_out );
     input [3:0] data_in ;
     input EN ;
     output [6:0] data_out ;
     reg [6:0] data_out ;
     or EN )
     begin
         data_out = 7'b ;
         if (EN == 1)
              case (data_in )
              endcase
     end
endmodule
4'b0000: data_out = 7'b ; // 0
4'b0001: data_out = 7'b ; // 1
4'b0010: data_out = 7'b ; // 2
4'b0011: data_out = 7'b ; // 3
4'b0100: data_out = 7'b ; // 4
4'b0101: data_out = 7'b ; // 5
4'b0110: data_out = 7'b ; // 6
4'b0111: data_out = 7'b ; // 7
4'b1000: data_out = 7'b ; // 8
4'b1001: data_out = 7'b ; // 9
4'b1010: data_out = 7'b ; // A
4'b1011: data_out = 7'b ; // b
4'b1100: data_out = 7'b ; // c
4'b1101: data_out = 7'b ; // d
4'b1110: data_out = 7'b ; // E
4'b1111: data_out = 7'b ; // F
default: data_out = 7'b ;
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39. Task 4: adder (3 bit) (use concatenate operator{})
module adder3(cout, sum, a, b, cin); input [2:0] a,b; input cin; output cout; output [2:0] sum; assign { cout, sum } = a + b + cin; endmodule
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40. Task 5: Comparator module compare2(eq,a,b); input [1:0] a,b;
output eq;
assign eq = (a == b)? 1:0 ;
endmodule
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41. Thank You
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