1. Foundations for Datapath Design
Chapter 5
B. Ramamurthy
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2. Background material (Review)
See Appendices in the CD: Esp. Appendix B for basics on basic combinational circuit design
Appendix B also has an introduction to Verilog
Lets review some Verilog material from Appendix B:
A wire specifies a combinational signal. A reg (register) holds a value, which can vary with time.
reg [31:0] X or wire [31:0];
Values can be 0, 1, z, x
4’b0100 specifies a 4-bit binary constant with the value 4, as does 4’d4.
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3. More on Verilog Example on “always”
initial constructs, which can initialize reg variables
continuous assignments, which define only combinational logic
always constructs, which can define either sequential or combinational logic
instances of other modules, which are used to implement the module being defined
Example on “always”
of signals that cause reevaluation)
begin
Verilog statements including assignments and other control statements
end
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4. Example for “always”
module Mult4to1 (In1,In2,In3,In4,Sel,Out); input [31:0] In1, In2, In3, In4; /four 32-bit inputs input [1:0] Sel; //selector signal output reg [31:0] Out;// 32-bit output In2, In3, In4, Sel) case (Sel) //a 4->1 multiplexor 0: Out <= In1; 1: Out <= In2; 2: Out <= In3; default: Out <= In4; endcase endmodule
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5. MIPS ALU
module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero; assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere A, B) //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1:0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; //default to 0, should not happen; endcase endmodule
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6. More on controlling the ALU
1. Place all combinational logic in a continuous assignment or an always block.
2. Make sure that all the signals used as inputs appear in the sensitivity list of an always block.
3. Ensure that every path through an always block assigns a value to the exact same set of bits.
The last of these is the easiest to overlook;
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7. Designing the Main Control Unit
Entry point for the design is Instruction set, types and format:
Three instruction formats: R-type, Branch, and load/store
The operation code, opcode field, is in [31:26] bits op[5:0]
The two registers to be read is specified by rs and rt; [25:21], [20:16]
Base register for load and store instruction is in rs, [25:21]
16-bit offset for the branch equal, load, and store is always in position [15:0]
The destination register is in one of the two places: for load it is in bit positions [20:16] (rt), for R-type instructions it is in [15:11] rd.
Thus we need a to add a multiplexer to select which field of the instruction is used to indicate the register number to be written.
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8. Instruction formats R-Type LW/SW Branch 4/8/2019 0 [31:26] rs [25:21]
rd [15:11]
shamt[10:6]
function[5:0]
LW/SW
35 or 43 [31:26]
address [15:0]
Branch
4 [31:26]
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9. Control Unit for the major ALU (Fig. 5.12)
Instruction Opcode LW SW
BEQ
R-Type
ALUop 00 01 10
Instruction operation
Load word
Store word
Branch equal
Add
Subtract
AND OR
Set on lessthan
Function Field
xxxxxx
100000
100010
100100
100101
101010
Desired ALU operation
add
subtract
and or
Set on lessthan
ALU Control input
0010
0110
0000
0001
0111
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10. Data Path Design DiagramS
Observe the incremental development in Figures
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