1. Clarifications regarding ADP 5091 eval board usage

2. Clarification 1: Board efficiency
PGOOD
Configuration used for testing the efficiency
GND
3.6 V
LDO – Disabled (GND)
GND
BAT Pin
3.6 V
Boost – Enabled(SYS)
GND
SYS Pin
3.6 V, 0.43mA
380 mV to CBP
GND
2.5 V
Reg_out Pin
380mV obtained by equation (1) of spec sheet
𝑉(𝑚𝑝𝑝𝑡)=𝑉(𝑂𝐶) 𝑅 𝑂𝐶1 𝑅 𝑂𝐶1 + 𝑅 𝑂𝐶2
Resistor values obtained from BOM of ADP 5091 Eval board
4.7 MΩ and 18 MΩ
𝜂= 𝑉𝑠𝑦𝑠 ∗𝐼𝑠𝑦𝑠 𝑉𝑖𝑛 ∗𝐼𝑖𝑛 = 35% K A
V(OC) = 463 mV
I(SC) = 9.63 mA
Solar cell block
The obtained efficiency is very much lower than the expected values

3. Clarification 2: ‘Reg_out’ pin voltage programming
R = 111 KΩ
(R selected from Table 7 of spec sheet)
Configuration used for testing the efficiency
VID
GND
LDO – Disabled (GND)
GND
BAT Pin
3.6 V
Boost – Enabled(SYS)
GND
SYS Pin
3.6 V, 0.43mA
MPPT sensing (MPPT)
GND
Reg_out Pin
2.5 V
The V_out should be 2 V, indicating the programmable feature is failing. K A
V(OC) = 463 mV
I(SC) = 9.63 mA
Solar cell block
Although the resister values are used as per table 7, the output voltages does nor follow the reported values

4. Clarification 3: Missing terminals
Some of the pins like MINOP , AGND etc have to be used while programming the threshold values, as per the equations. The board does not have terminals for external communication.
Solar cell block information
The solar cell block which has been used in the experiments is a Si based solar cell module. It features24 white LED’s bank, serving as light source for solar cells, enclosed in black box. The LED’s can be biased at two different voltage levels through terminals I1 and I2 (as shown below). I2 has been used in our testing, as it gives higher voltage and current outputs of solar cells. For the biasing voltage of 12 V thru I2 terminal, the block generates open circuit voltage of ≈ 470mV (Voc) and short circuit current of ≈ 10 mA (Isc).