1. TCAD Simulation and test setup For CMOS Pixel Sensor based on a 0
TCAD Simulation and test setup For CMOS Pixel Sensor based on a 0.18 μm technology
李龙 刘剑 张亮 董家宁 王萌
Shandong University
Hengyang , Oct. 16th ,2018
2019/4/7

2. Outlines Background and motivation
Brief introduction of TCAD simulation
CMOS Pixel Sensor simulation work based on a 0.18 μm technology
Chip test for the sensor simulated
Summary
2019/4/7

3. Background and motivation
R [mm]
Vertex
Silicon Tracker
Layout of CEPC vertex and Silicon Tracker
Z [mm]
A Tower Jazz 0.18μm technology is going to be applied on CEPC Silicon Tracker. In order to reach the spatial resolution of 7μm,the Charge Collection Efficiency and Diode capacitance which matter much in SNR should be simulated before chip design.
This talk is about the simulation work and test setup for a CMOS Pixel Sensor based on Tower Jazz 0.18 μm technology.
2019/4/7

4. Chip design The chip contains: 9 submatrices Each matrix: 16*64
Rolling shutter readout mode
32 μs integration time at 2MHz clock frequency
16 parallel analog outputs
sensitive area: 2*7.88 𝒎𝒎 𝟐
2019/4/7

5. About TCAD
Technology Computer Aided Design(TCAD) is a branch of electronic design automation that models semiconductor fabrication and semiconductor device operation.
The simulation tool we use is Sentaurus which belongs to SYNOPSYS Inc.
Tools used for the simulation in TCAD sentaurus
2019/4/7

6. Types and geometry of sensors
HR: 200 μm 1 Ω·cm substrate with 18 μm 1 kΩ·cm EPI-layer
CZ(Czochralski process): 218 μm 700Ω·cm substrate
21μm*21μm pitch
42μm*21μm pitch
84μm*21μm pitch
2019/4/7

7. Charge Collection with MIPs
Comparison of Charge Collection Bias Voltage -1.5V
Charge Collection with MIPs
Charge Collection for 90% charge collecting time ( 𝒆 − ) HR CZ
Total
Seed Pixel
21μm*21μm
1850
691
1191
585
42μm*21μm
1478
714
958
591
84μm*21μm
1232
731
801
596
Charge Collection of HR_21μm*21μm Bias Voltage -1.5V
Pixel_33
(seed pixel)
90% Charge Collecting Time (ns) HR CZ
21μm*21μm 84 39
42μm*21μm
105 51
84μm*21μm
130 54
Pixel information
N(D)=number of diode in each pixel:1
F(D)=footprint of diode(diode area and pwell opening):11 𝝁𝒎 𝟐
S(D)=surface of diode: 8 𝝁𝒎 𝟐
2019/4/7

8. Diode Capacitance NW Capacitance (fF) HR 4.0 CZ EPI-layer
Capacitance comparison Bias Voltage -1.5V
Capacitance (fF) HR
4.0 CZ
EPI-layer
2019/4/7

9. Test setup for the sensor charge gain calibration
FPGA board
DUT board
Sensor type (HR) PC
Main board
Fe-55
2019/4/7

10. Sensor response to Fe-55 Clock(2MHz) Persistence Mode(infinite)
Normal Mode
10 mV Voltage drop due to X-rays
Offset
Frame_Out
2019/4/7

11. Corelated Double Sampling with Oscilloscope
-Trigger： Frame_Out（every 32 μs).
-Record：Voltage of a column pixel for 2 frames.
-Sampling time: 30 mins.
-Sampling rate: 500MS/s.
64 μs (2 frames）
2019/4/7

12. Result of CDS
Noise Measurement
-Only 4 of 64 a column pixels(64) capture the signal, and the voltage drops vary from 8mV to 18mV, more data needed to calibrate the sensor charge gain using 5.9 KeV peak.
-The measured noise is about 1.12 mV which is reasonable.
-This method is time consuming and inefficiency since the data lose during the file saving.
-CDS with ADC is on going.
Output of the pixels which capture signals (Absolute values)
2019/4/7

13. Summary
~2 types of sensors have been simulated , simulated values of Charge Collection and Diode Capacitance were given.
~Optimized geometry and sensor type were HR and 21μm*21μm，need test data to verify.
~CDS with ADC is on going.
~A telescope project has been applied by SDU Pixel group, and another 0.18μm technology will be applied, these simulation and test result would be a guidance for next chip design.
2019/4/7