1. Carlos Mariñas, IFIC, CSIC-UVEG DEPFET Technology for future colliders Carlos Mariñas IFIC-Valencia (Spain) 1 LCPS09, Ambleside

2. Carlos Mariñas, IFIC, CSIC-UVEG DEPFET (DEpleted P-channel Field Effect Transistor): Technology invented by J. Kemmer & G. Lutz, 1987  J. Kemmer and G. Lutz: ''New semiconductor detector concepts'', Nucl. Instr. & Meth. A 253 (1987) 365-377 DEPFET (DEpleted P-channel Field Effect Transistor): Technology invented by J. Kemmer & G. Lutz, 1987  J. Kemmer and G. Lutz: ''New semiconductor detector concepts'', Nucl. Instr. & Meth. A 253 (1987) 365-377 Several different applications for Astrophysics and Particle Physics:  XEUS : Future european X-ray observatory to investigate the Early Evolution Stages of the Universe (early black holes, evolution of galaxies…)  BepiColombo : ESA project to Mercury to investigate the origin and evolution of the planet  X-FEL  ILC  BELLE-II → Technology chosen for the new Vertex Detector Several different applications for Astrophysics and Particle Physics:  XEUS : Future european X-ray observatory to investigate the Early Evolution Stages of the Universe (early black holes, evolution of galaxies…)  BepiColombo : ESA project to Mercury to investigate the origin and evolution of the planet  X-FEL  ILC  BELLE-II → Technology chosen for the new Vertex Detector LCPS09, Ambleside 2

3. Why this technology? Carlos Mariñas, IFIC, CSIC-UVEG  Vertexing in future colliders requires excellent vertex reconstruction and efficient heavy quark flavour tagging See Prof. Ch. Damerell’s talk  Vertexing in future colliders requires excellent vertex reconstruction and efficient heavy quark flavour tagging See Prof. Ch. Damerell’s talk  This requirements impose unprecedented constraints on the detector: High granularity to cope with the high density of tracks in the jets and the background High spatial resolution per layer <4  m (pixel size of 25x25  m 2 ) Fast read-out Low material budget: <0.1%X 0 /layer (~100  m of Si) Low power consumption  This requirements impose unprecedented constraints on the detector: High granularity to cope with the high density of tracks in the jets and the background High spatial resolution per layer <4  m (pixel size of 25x25  m 2 ) Fast read-out Low material budget: <0.1%X 0 /layer (~100  m of Si) Low power consumption DEPFET  Measurements made on realistic DEPFET prototypes have demonstrated that the concept is one of the principal candidates to meet these challenging requirements DEPFET  Measurements made on realistic DEPFET prototypes have demonstrated that the concept is one of the principal candidates to meet these challenging requirements LCPS09, Ambleside 3

4. The DEPFET principle Carlos Mariñas, IFIC, CSIC-UVEG  Each pixel is a p-channel FET on a completely depleted bulk (sideward depletion). Charge is collected by drift  A deep n-implant creates a potential minimum for electrons under the gate (internal gate)  Each pixel is a p-channel FET on a completely depleted bulk (sideward depletion). Charge is collected by drift  A deep n-implant creates a potential minimum for electrons under the gate (internal gate) o Small pixel size ~25μm o r/o per row ~50ns (20MHz) (drain) Fully depleted bulk o Noise≈100e -  Small capacitance and first in-pixel amplification o Thin Detectors≈50μm o Small pixel size ~25μm o r/o per row ~50ns (20MHz) (drain) Fully depleted bulk o Noise≈100e -  Small capacitance and first in-pixel amplification o Thin Detectors≈50μm  Signal electrons accumulate in the internal gate and modulate the transistor current (g q ≈500pA/e - )  Accumulated charge can be removed by a clear contact  Signal electrons accumulate in the internal gate and modulate the transistor current (g q ≈500pA/e - )  Accumulated charge can be removed by a clear contact GOAL  Internal amplification  Low power consumption: Readout on demand (Sensitive all the time, even in OFF state)  Internal amplification  Low power consumption: Readout on demand (Sensitive all the time, even in OFF state) LCPS09, Ambleside 4

5. p+ n+ rear contact drainbulksource p s y m m e t r y a x i s n+ n internal gate top gateclear n - n+ p+ FET-Transistor integrated in every pixel (first amplification) Electrons are collected in „internal gate“ and modulate the transistor-current Signal charge removed via clear contact - - + + + + - MIP internal Gate Potential distribution: Drain Source Backcontact [TeSCA-Simulation] ~1µm 50 µm - - -- -- DEPFET-Principle of Operation Carlos Mariñas, IFIC, CSIC-UVEG LCPS09, Ambleside 5

6. p+ n+ rear contact drainbulksource p s y m m e t r y a x i s n+ n internal gate top gateclear n - n+ p+ FET-Transistor integrated in every pixel (first amplification) Electrons are collected in „internal gate“ and modulate the transistor-current Signal charge removed via clear contact internal Gate Potential distribution: Drain Source Backcontact [TeSCA-Simulation] ~1µm 50 µm - - -- -- DEPFET-Principle of Operation Carlos Mariñas, IFIC, CSIC-UVEG 0V +20V 0V LCPS09, Ambleside

7. ILC prototype system Carlos Mariñas, IFIC, CSIC-UVEG Hybrid Board DEPFET 64x256 matrix Readout chip (CURO) Steering chips (Switchers) Hybrid Board DEPFET 64x256 matrix Readout chip (CURO) Steering chips (Switchers) Readout Board 16 bit ADCs  Digitization XILINX FPGA  Chip config. and synchronization during DAQ 128 kB RAM  Data storage USB 2.0 board  PC comm. Readout Board 16 bit ADCs  Digitization XILINX FPGA  Chip config. and synchronization during DAQ 128 kB RAM  Data storage USB 2.0 board  PC comm. Protection Board Regulators Protection Board Regulators LCPS09, Ambleside 6

8. Hybrid board Carlos Mariñas, IFIC, CSIC-UVEG DEPFET Matrix 64x128 pixels Several pixel sizes, implants, geometries DEPFET Matrix 64x128 pixels Several pixel sizes, implants, geometries Switchers: Steering chips Gate: Select row Clear: Clear signal Switchers: Steering chips Gate: Select row Clear: Clear signal CURO: 128 channels CUrrent Read Out Subtraction of I ped from I ped +I sig CURO: 128 channels CUrrent Read Out Subtraction of I ped from I ped +I sig LCPS09, Ambleside 7

9. Operation mode: Row wise readout Carlos Mariñas, IFIC, CSIC-UVEG Row wise r/o (Rolling Shutter)  Select row with external gate, read current, clear DEPFET, read current again  The difference is the signal  Low power consumption: Only one row active at a time; Readout on demand (Sensitive all the time, even in OFF state)  Two different auxiliary chips needed (Switchers)  Limited frame rate Row wise r/o (Rolling Shutter)  Select row with external gate, read current, clear DEPFET, read current again  The difference is the signal  Low power consumption: Only one row active at a time; Readout on demand (Sensitive all the time, even in OFF state)  Two different auxiliary chips needed (Switchers)  Limited frame rate DEPFET-matrixGate SWClear SW Drain Enable row – Read current (I sig + I ped ) – Clear – Read current (I ped ), Subtract – Move to next row LCPS09, Ambleside 8

10. DEPFET Concept for a half ILC module Carlos Mariñas, IFIC, CSIC-UVEG  10 and 25 cm long ladders read out at the ends  24 micron pixel  design goal 0.1% X 0 per layer in the sensitive region LCPS09, Ambleside 9

11. Thinning : mechanical samples Carlos Mariñas, IFIC, CSIC-UVEG 6” wafer with diodes and large mechanical samples Thinned area: 10cm x 1.2 cm (ILC vertex detector dummy) Possibility to structure handling frame (reduce material, keep stiffness) LCPS09, Ambleside 10

12. Telescope: 5 DEPFET planes 32x24 μm 2 CCG 450 μ m thick Telescope: 5 DEPFET planes 32x24 μm 2 CCG 450 μ m thick DEPFET achievements: Test Beam Setup BEAM 120 GeV ∏ DUT: 1 DEPFET modules Various pixel sizes 450 μ m thick DUT: 1 DEPFET modules Various pixel sizes 450 μ m thick Scintillators: 1 Big “Beam finder” 1 Finger “Beam allignment” Triggering Scintillators: 1 Big “Beam finder” 1 Finger “Beam allignment” Triggering Carlos Mariñas, IFIC, CSIC-UVEG Trigger Synchronization via TLU (Trigger Logic Unit) x y z LCPS09, Ambleside 11

13. Test Beam Setup Carlos Mariñas, IFIC, CSIC-UVEG General view 6 Modules at once 1 rotating module General view 6 Modules at once 1 rotating module LCPS09, Ambleside 12

14. My work Carlos Mariñas, IFIC, CSIC-UVEG  Calibration/optimization of different generations of matrices: PXD4-Clocked Cleargate. 128x64 pixels PXD5-Common Cleargate. 128x64 pixels PXD5-Capacitative Coupled Cleargate. 256x64 pixels  Calibration/optimization of different generations of matrices: PXD4-Clocked Cleargate. 128x64 pixels PXD5-Common Cleargate. 128x64 pixels PXD5-Capacitative Coupled Cleargate. 256x64 pixels LCPS09, Ambleside 13

15. Carlos Mariñas, IFIC, CSIC-UVEG  Test Beam Data analysis (SNR, Residuals, Charge collection uniformity)  Test Beam Data analysis (SNR, Residuals, Charge collection uniformity) Preliminary ResY=1.34 μm 3x3 cluster signal σ≈4% LCPS09, Ambleside 14

16. Carlos Mariñas, IFIC, CSIC-UVEG Natural convection  Mechanical/Thermal measurements and simulation (Finite Element An.) Natural frequencies, self weigth bowing, deformations Conduction, convection, thermal stress Power cycling Thermal characterization of different materials for cooling (Al, Cu, TPG)  Mechanical/Thermal measurements and simulation (Finite Element An.) Natural frequencies, self weigth bowing, deformations Conduction, convection, thermal stress Power cycling Thermal characterization of different materials for cooling (Al, Cu, TPG) LCPS09, Ambleside 15

17. Thank you very much! Carlos Mariñas, IFIC, CSIC-UVEG The LHC is not the end… but just the beginning! Belle-II, SuperB, ILC, CLIC… LCPS09, Ambleside 16