1. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University A DEPFET pixel-based Vertexdetector for TESLA 55. PRC -MeetingHamburg, Mai 2003 M. Trimpl University of Bonn M.Karagounis, R.Kohrs, H.Krüger, I.Peric, M.Schumacher, M.Trimpl, J.Ulrici, N.Wermes University of Mannheim P. Fischer, M.Harter MPI Munich, HLL L.Andricek, G.Lutz, R.H.Richter, M.Schnecke-Radau MPE Garching, HLL S.Herrmann, G.Schaller, F.Schopper, L.Strüder, J.Treis PNSensor GmbH, HLL K.Heinzinger, P.Lechner, H.Soltau

2. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University C ONTENT  Vertex Detection at TESLA  The DEPFET Principle  DEPFET pixels for TESLA  Present Status - detector - thinning - Switcher (steering) - CURO (readout)  Summary

3. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University Vertex Detection at TESLA  geometry: same for all proposals pixel size: 20-30 µm close to IP, r = 15 mm (efficient c-tagging) high spatial resolution: few µm 5 barrels – stand alone tracking thinned sensor: d = 50µm, ~0.1% X 0 overall: ~ 1GPixel 50µs readout time for module / detector Required clock rate: up to 50MHz for TESLA @ Layer I  time structure high e + e - -background: 80 hits / (mm 2 train)

4. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University C ONTENT  Vertex Detection at TESLA  The DEPFET Principle  DEPFET pixels for TESLA  Present Status - detector - thinning - Switcher (steering) - CURO (readout)  Summary

5. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University p+ n+ rear contact drainbulksource p s y m m e t r y a x i s n+ n internal gate top gateclear n - n+ p+ DEPFET-Principle of Operation  FET-Transistor integrated in every pixel (first amplification)  Electrons are collected in „internal gate“ and modulate the transistor-current  Signal charge removed via clear contact - - + + + + - MIP internal Gate Potential distribution: Drain Source Backcontact [TeSCA-Simulation] ~1µm 50 µm - - -- --

6. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University p+ n+ rear contact drainbulksource p s y m m e t r y a x i s n+ n internal gate top gateclear n - n+ p+ DEPFET-Principle of Operation  FET-Transistor integrated in every pixel (first amplification)  Electrons are collected in „internal gate“ and modulate the transistor-current  Signal charge removed via clear contact internal Gate Potential distribution: Drain Source Backcontact [TeSCA-Simulation] ~1µm 50 µm - - -- -- 0V +15V 0V

7. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University read pedestal current reset pixel / clear internal gate (row wise) read pixel-current at drain Matrix Operation Matrix-scheme:  64 x 64 matrix with 50 x 50 µm 2 pixel  designed for Biomedical Applications  clock rate : 50 kHz  achieved noise in matrix: ~100e - (due to operation mode) DEPFET-Hybrid: Control-Chip: Switcher I 64x64 pixel DEPFET-Matrix (50x50µm 2 pixel) low noise Readout-Chip: CARLOS

8. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University achieved performance Single-pixel spectra: ENC = 4.8 +/- 0.1 e - 55 Fe-spectra @ 45  C [J.Ulrici, Bonn] Autoradiogram with 3 H: ~ 10 mm detection of Tritium 3 H (5,6 keV mean energy) spatial resolution (50x50 µm 2 pixel): ~ 4.5µm (22 keV, 109 Cd) ~ 6.5µm (6 keV, 55 Fe) ~ 3.2 mm Matrix-picture with 55 Fe: measured at room temperature

9. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University C ONTENT  Vertex Detection at TESLA  The DEPFET Principle  DEPFET pixels for TESLA  Present Status - detector - thinning - Switcher (steering) - CURO (readout)  Summary

10. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University DEPFET-Pixels for TESLA Layer I - Module: attractive features for TESLA: small pixel size (20-30µm) low noise  thin (50µm)  S/N > 70 @ RT - thin sensor (50µm) + frame   0.11% X 0 / layer low power consumption  little cooling ! - in active area : sensor + R/O chip or steering chip - whole vtx-d (5 layers / pulsed mode ) : sensor : 0.3W steering: ~ 3-4 W R/O chip: 1-2 W frame: ~300µm sensor: ~50µm whole vtx-d: ~5W

11. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University DEPFET-Pixels for TESLA attractive features for TESLA: small pixel size (20-30µm) low noise  thin (50µm)  S/N > 70 @ RT - thin sensor (50µm) + frame   0.11% X 0 / layer low power consumption  little cooling ! - in active area : sensor + R/O chip or steering chip - whole vtx-d (5 layers / pulsed mode ) : sensor : 0.3W steering: ~ 3-4 W R/O chip: 1-2 W whole vtx-d: ~5W perforated frame for reduced material

12. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University steps towards TESLA :  new DEPFET-sensor fabrication -  smaller pixels (25µm)  improved performance for TESLA  develop thinning of sensors -  fast (50 MHz) steering chip -  fast readout chip with 0 suppression -  (full size) prototype system finished first results fabricated prototype

13. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University C ONTENT  Vertex Detection at TESLA  The DEPFET Principle  DEPFET pixels for TESLA  Present Status - detector - thinning - Switcher (steering) - CURO (readout)  Summary

14. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University new sensors for TESLA  from JFETs to MOSFETs  less device variation (large sensors), linear transistors (small pixels)  double metal process (large sensors)  higher amplification (1nA/e - )  fast and complete clear clear contacttransistor channel clear gate new sensors: Potential distribution (1µm depth) [Poseidon 3d – Simulator] clear contact internal gate potential energy [eV] double pixel-cell

15. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University new fabrication just finished (April 2003)... 16x128 DEPFET-Matrix double pixel cell 33 x 47 µm 2 in DEPFET-Matrix drain gate reset

16. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University new fabrication just finished (April 2003)... double pixel cell 33 x 47 µm 2 in DEPFET-Matrix drain gate reset First measurements:  diode leakage current: ~ 300pA/cm² (fully depleted)  pixel transistor: V TH ~ 0V : Device can be completely switched off.  Step to MOSFETs successful

17. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University DEPFET thinning [L. Andricek, MPI Munich] TESLA-Module („dummy“ sample) 50µm silicon with 350µm frame thinned diode structures: leakage current: <1nA /cm 2 d) anisotropic etching from backside (TMAH) open backside passivation c) process  passivation b) wafer bonding and grinding/polishing of top wafer a) oxidation and back side implant of top wafer Handle Wafer Top Wafer

18. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University new steering chip AMS 0.8µm HV versatile sequencing chip (internal sequencer  flexible pattern) high speed + high voltage range (20V) drives 64 DEPFET-rows (can be daisy chained) produced 12/2002 Switcher II: [I.Peric (Bonn) / P.Fischer (Mannheim)] 4.6 mm 4.8 mm Results: power consumption: ~1W /channel tested ok to 30MHz

19. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University Current based Readout Storage phase: input and sample-switch closed :  gate-capacitance of nmos charged I STORE Transfer phase: output switch closed : (done immediately after sampling)  I STORE is flowing out Sampling phase: input and sample-switch opened :  voltage at capacitance „unchanged“  current unchanged I = I In + I Bias How to store a current ??

20. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University CURO - Architecture  front end: automatic pedestal subtraction (double correlated sampling) - easy with currents -  analog currents buffered in FIFO  Hit-Logic performs 0 suppression and multiplexes hits to ADC (ADC only digitizes hits !) CURO : CUrrent Read Out

21. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University Results - CURO I  TSMC 0.25µm, 5metal  contains all blocks for a fast DEPFET R/O  radiation tolerant layout rules with annular nmos  produced 05/2002 CURO I: analog part (current memory cell): tested up to: 25MHz differential non-linearity: 0.1 % noise contribution to readout: < 39e - digital part: works with desired speed (50MHz) crucial elements of readout concept work 4 mm 1.5 mm

22. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University Prototype System Hybrid-PCB: steering chips for Gate and Reset (Switcher II) 64x128 pixel DEPFET-Matrix 128 channel R/O – Chip (CURO II) - submission scheduled: july 2003 - improved sampling speed : 50MHz - analog noise contribution : < 30 e - - linearity well below 1% Readout-PCB: ADC and RAM communication between Hybrid and PC

23. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University Summary main DEPFET features  high S / N ~ 70,  high spatial resolution (~2 µm, analog readout)  thin (50 µm)  low power (< 5W total, pixel inactive during charge collection)  current based fast readout (50 MHz)

24. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University Outlook  2nd version of readout chip (CURO II): july 2003  study new DEPFET structures: summer 2003  system assembly: 2nd half of 2003  radiation hardness issues  prototype system  full size TESLA Module

25. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University

26. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University Power consumption R/O Chip: 2mW / channel  200 W (whole vtx-d) Number of R/O channels @ TESLA: L1 : 520x2x8 = 8320 L2-5: (880x2)x(8+12+16+20) = 98560 All: 106880 channels Sensor: P DEPFET = 5V x 100 µA = 500µW  50 W Steering: 0.94mW /channelDC, 3.13mW / channel @ 50MHz L1 : 2x3.13 + (3998x0.94) mW= 34W L2-5: [2*3.13 + (13538x0.94)] x (8+12+16+20) mW = 713W  All: 747 W All : 997W, 1/199 duty cycle : 5W

27. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University material budget Estimated Material Budget (1 st layer): Pixel area: 100x13 mm 2, 50  m : 0.05% X 0 steer. chips: 100x2 mm2, 50 mm : 0.008% X 0 (massive) Frame :100x4 mm 2, 300  m : 0.09% X 0 reduce frame material!!! by etching of "holes" in the frame perforated frame: 0.05 % X 0 total: 0.11 % X 0 5-layer (CCD-like) layout for the vertex detector 1 st layer module: sensitive area 100x13 mm 2 sensitive area thinned down to 50  m, supported by a directly bonded 300  m thick frame of silicon

28. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University Performance of Prototype R/O Chip analog part (memory cell): speed: 25MHz accuracy: 0.1 % noise : < 30 electrons digital part: the hit-finder and the current-comparator-block both work with desired speed (50MHz) 0.1% accuracy reached

29. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University different readouts Layer I:Layer II..V:

30. Hamburg, 07.05.2003 Marcel Trimpl, Bonn University Background at TESLA High magnetic field to „reduce“ background But still: Rate high ( 80 hits / mm bunchtrain ) One frame per Train: Occupancy 20% !!!!! Simulation : [C.Büssser, DESY]