1. OmegaPix 3D IC prototype for the ATLAS upgrade SLHC pixel project 3D Meeting 19th March, A. Lounis, C. de La Taille, N. Seguin-Moreau, G. Martin-Chassard, D. Thienpont (LAL Orsay)

2. Outline Goals OmegaPix Up-coming work Analog tier « Digital » tier
Tests and measurements
Up-coming work
February 24, 2019
D. Thienpont ATLAS LAL

3. OmegaPix is a first prototype dedicated to two main goals:
Firstly: study and validate the new Chartered techno and the 3D process
Tiers isolation, Chartered techno characterization (T typical, low Vt), yield, electrical and mechanical connections
Secondly: explore new solutions for the pixel chip for the ATLAS upgrade
low power, small pitch, low signal
February 24, 2019
D. Thienpont ATLAS LAL

4. Goals: Aggressive requirements
Study variants of blocks for FEI4 or FETC4 (preamp, discri, DAC, local storage and readout)
Alternative approach using 3D possibilities to :
Better granularity: smaller pixels (50x50µm instead of 50x250)
New analog front-end designed to decrease the power dissipation, lower the threshold
Minimize dead zones in periphery, and between each chip
Digital substrate isolation from analog one (not still implemented)
Match new MPI Munich Pixel sensor matrix
Target 3 µW/ch: 2 µW/ch for the analogue tier, 1 µW/ch for the digital one
Low threshold (1000 e-), low noise (100 e-)
Need to minimize thickness in order to keep the 3D
advantages
February 24, 2019
D. Thienpont ATLAS LAL

5. OmegaPix
Omegapix embeds a matrix of 1536 pixels distributed in 24 columns and 64 rows
Several different columns have been designed to characterize various flavours of transistors (typical, lowVt, 3p3) and to study the noise contribution from one tier on the other
Columns 1 to 10: reference channels
Columns 11 to 18: various preamplifier transistor types have been integrated
Columns 19 to 22: without variable gain
Column 23: discriminator has been removed
Column 24: shaper has been removed
Chip size
Height= 4.08 mm, Width =1.74 mm,
Area = 7.1 mm²
Power Supply: 1V / 1.2 V
OmegaPix
Analog
OmegaPix
Digital
February 24, 2019
D. Thienpont ATLAS LAL

6. OmegaPix: analog tier
To minimize power dissipation, power voltage has been reduced to 1.2 V for the analog part and 1 V for the digital (with the discri)
Discri is performed by three inverters, and to fix the threshold we use a DAC 5bits which tune the DC level at the output of the shaper
February 24, 2019
D. Thienpont ATLAS LAL

7. OmegaPix: Analogue tier – Charge preamplifier
Parasitic capacitance Cgd performs the feedback capacitance: Cf = Cgd ≈ 1,6 fF. Ideal gain is 1/Cf -> 625 mV/fC
A paraphase structure has been used to fix the DC points and absorb the leakage current coming from the detector
VDD = 1,2 V
Cgd not precise: need of gain adjustment
Paraphase structure
Ib1 = 1 nA, Ib2 = 2 nA, Ib3 = 1 µA
February 24, 2019
D. Thienpont ATLAS LAL

8. OmegaPix: Analogue tier - Shaper
Ib1 = 2.5 nA, Ib2 = 5 nA, Ib3 = 50 nA
A shaper variable gain has been designed; four different NMOS transistors can be switched in parallel which leads to make Cgd value to vary
DAC fixes the output DC voltage
February 24, 2019
D. Thienpont ATLAS LAL

9. OmegaPix: Analogue tier - DAC 5 bits
The DAC fixes the treshold voltage
In fact, only 4.5 bits
DAC voltage output
bits
February 24, 2019
D. Thienpont ATLAS LAL

10. OmegaPix: typical simulation
Simulation conditions: Qinj = 1000 e-
DAC: 1000 (only 2.5/0.5 nmos_1p5_lvt as shaper), Vth = 800 mV
Transient response
Noise at the output of the shaper
Shaper
DAC fixes the DC shaper output voltage and so the threshold
DAC: 1000
Vth = 800 mV
282 mV
S/N =
Noise threshold = 50 e- to 130 e-
Preamplifier
Vmax = Q/C => 60 mV
59.6 mV
2 MHz
February 24, 2019
D. Thienpont ATLAS LAL

11. OmegaPix: « Digital » tier
Digital tier has been designed by Yixian Guo from LPNHE (Paris). Each channel includes a 24 DFlipflop register: main tests will focus about the noise study
Read bus on out pad
Go to the next channel D_r pin
Q_r
D_r
1536 channels, 24 columns, 64 ch/col
64 channels
Q_r
D_r
Only one channel output can be viewed on the same time
Q_r
D_r
out
24 columns
February 24, 2019
D. Thienpont ATLAS LAL

12. OmegaPix: dedicated test chip – Slow Control
24 columns, 64 channels/columns -> 1536 channels
14 SC bits/channel -> SC bits
2 SC bits/selectColumn -> 48 bits
SC in the entire analog matrix
In_test -> 1 bit
3 probes: preamplifier, shaper, discriminator -> 3 bits
DAC -> 5 bits
Shaper: variable gain -> 4 bits
Discriminator: mask -> 1 bit
-> 14 SC bits / channel
Slow control bits for one analog channel
February 24, 2019
D. Thienpont ATLAS LAL

13. Measurements and up-coming work
- Firmware and LabView software are OK
- Four test boards are wired
Measurements
Analog tier: preamp, shaper, discri + noise
threshold dispersion
Digital tier
Layers coupling
Chartered/Tezzaron techno characterization: transistor (LowVt, 3p3, 1p5, size), DAC linearity…
Up-coming work
- Digital readout study and design with channel pitch 50x50um requirement: clustering, charge measurement, readout policy, digital gates rad-hard
test board with sensor from Munich
- 2D run possibility
February 24, 2019
D. Thienpont ATLAS LAL

14. Thank you for your attention
February 24, 2019
D. Thienpont ATLAS LAL

15. backup Injected charge (e-) 100 625 930 1000 1250 1560 3125 4375 6250
February 24, 2019
D. Thienpont ATLAS LAL

16. ToT and TW
February 24, 2019
D. Thienpont ATLAS LAL

17. Dynamic memory
The dynamic memory stores all events even if no hit appears. When we write into a cell, the next is read. If there is a hit and if there is L1 trigger, then we keep this hit into a RS FlipFlop. Two fast OR are sent across the column and across the row.
Bus_write
BC0
BC1
BC2
BC3
BC(n-1)
BCn
or_column
vdd
Switches commands are common for all the matrix
or_row
L1 trigger
Select_row
120 memory cells for each channel
120 x 25 ns = 3 us
Select_col
Raz_sm
Layout almost OK
February 24, 2019
D. Thienpont ATLAS LAL

18. Readout scheme
clock
All triggered pixels have to be readout in less than 125 ns with this configuration ! L1
(1) Logic finds the rightmost column with hit and stores Then it select this column.
(2) Logic finds the rightmost pixel with hit and stores Then RSFF is erased.
7 clocks to readout a triggered hit.
Logic readout all the matrix or a sub-matrix.
February 24, 2019
D. Thienpont ATLAS LAL