Presentation on theme: "Programmable Logic Devices and Architectures: A Nano-Course"— Presentation transcript:
1 Programmable Logic Devices and Architectures: A Nano-Course R. KatzGrunt EngineerNASA
2 What We Will Cover Various programmable logic types Device architecturesDevice performancePackagingReliabilitySome radiation considerationsLessons learned
3 What You Will Not LearnYou will not learn much. This course is only a brief introduction to key concepts and issues, not a comprehensive and in-depth tutorial.Because of time limitations, sections have been either scaled back or eliminated.
4 References References are available for most slides Original work available onManufacturers’ data sheets, application notesPapers and reportsMany from MAPLD 1998, 1999, 2000Standard logic design textbooks
5 Barto's Law: Every circuit is considered guilty until proven innocent. Lessons Learned (1)Barto's Law: Every circuit is considered guilty until proven innocent.
6 Lessons Learned (2)Launched: March 4, 1999Failed: March 4, 1999
7 Applications Some Application Types Existing SSI/MSI IntegrationObsolete/"Non-Space-Qualified" Component ReplacementBus Controllers/InterfacesMemory Controller/ScrubberHigh-Performance DSPProcessorsSystems on ChipMany Other Digital Circuits
18 Summary of Current Technology Type Re-programmable Volatile Technology Radiation HardnessFuse No No Bipolar HardEPROM Yes No UVCMOS ModerateEEPROM YES, ICP No EECMOS ModerateSRAM YES, ICP Yes CMOS SoftAntifuse No No CMOS HardFRAM Yes, ICP No Perovskite Hard1FerroelectricCrystal1Get Bennedetto paper to verify.
19 FPGA Architecture Assembly of Fundamental Blocks HierarchicalIntegration of Different Building BlocksLogic (Combinational and Sequential)Dedicated Arithmetic LogicClocksInput/OuputDelay Locked LoopRAMRouting (Interconnections)Channeled ArchitectureSea-of-Module Architecture
28 Act 2 Logic Module: C-Mod 8-Input Combinational function766 possible combinationalmacros11”Antifuse Field Programmable Gate Arrays,” J. Greene, E. Hamdy, and S. Beal,Proceedings of the IEEE, Vol. 91, No. 7, July 1993, pp
29 Act 2 Flip-flop Implementation Feedback goes throughantifuses (R) and routingsegments (C)Hard-wired Flip-flopRouted or “C-C Flip-flop”
43 Act 1Many families have slew rate control to limit signal reflections and ground bounce.Different families drive their outputs to different levels.
44 Different I/O Standards Virtex 2.5V Example I/O Standard Input Ref Output Board VVoltage Source Termination Tolerant(VREF) Voltage Voltage(VCCO) (VTT)LVTTL 2–24 mA N/A N/A YesLVCMOS N/A N/A YesPCI, 5 V N/A N/A YesPCI, 3.3 V N/A N/A NoGTL N/A NoGTL N/A NoHSTL Class I NoHSTL Class III NoHSTL Class IV NoSSTL3 Class I &II NoSSTL2 Class I & II NoCTT NoAGP N/A No
46 Deterministic Power-up SX-S Example VCCAVCCIPull-ups /downs are selectable on an individual I/O basisPull-up follows VCCIPull-downs and pull-ups are dis- abled 50 ns after VCCA reaches 2.5V and therefore do not draw current during regular operation.Once VCCA is powered-up, 50ns is required for a valid signal to propagate to the outputs before the pull-ups /downs are disabledRTSX-SPull-up enabledPREInput Driven low or external POR SignalCLRPull-down enabled
47 Cold Sparing - SX-S Powered-up 3.3/5 Volts Powered-down Board 0 Volts RTSX-SVCCIGND0 Volts3.3/5 VoltsActive Bus orBackplanePowered-downBoardPowered-upI/O w/ ” Hot-Swap”Enabled does notsink current
50 Shielded Packages - Rad-Pak™ This package, with tie bar, 24 gramsShielding thickness may vary between lotsShield is 10-90/copper-tungstenDensity of shield is ~ 18 g/cm3 (need to verify)EEPROMs and other devices also packaged similarly
51 Spot Shielding Qualification Board - Maximum Thickness
54 Nominal Lead/Ball Pitch CQ "CQ "CQ "CQ "CQ mmPQ mmCQ mmCG mmNote: Pin spacing for PGAs is typically 0.1"
55 Mass Characteristics Approximate values (in grams) CQCQCQCQCQCQPQCBCQCQPGPGPGPGPG1BGCG11With heat sink. Over the years, there has been a lot of variation as to which parts have heat sinks. Check each package.
56 Reliability Introduction to Reliability Historical Perspective Current DevicesTrends
57 The Bathtub Curve Time Failure rate, Constant Useful life Wear out InfantMortality
58 Introduction to Reliability Failure in time (FIT)Failures per 109 hours( ~ 104 hours/year )Acceleration FactorsTemperatureVoltage
59 Introduction to Reliability (cont'd) Most failure mechanisms can be modeled using the Arrhenius equation.ttf - time to failure (hours)C - constant (hours)EA - activation energy (eV)k - Boltzman's constant (8.616 x 10-5eV/°K)T - temperature (ºK)ttf = C • eEA/kT
66 Thermal Performance Package modeled as a resistance Junction temperature the critical parameterOften derated to ~ 100 ºCtJ = P • J-CtJ = Junction temperature in ºCP = Power in wattsJ-C = thermal resistance, junction to case, in ºC/watt
67 Thermal Performance - Devices J-C for Flight Devices in ºC/watt Ceramic Pin Grid ArrayPGPGPGPGPGNotes:1These packages are cavity down.2With embedded heat spreader3Estimated4TypicalCeramic Quad Flat PackCQCQCQCQCQCQOtherPQ /3.82PQHQCG
74 Model Direct Connect Fast Connect Hardwired StructuresActel RoutingModel Direct Connect Fast Connect(ns) (ns)RT54SXRT54SXSVirtex Carry ChainTBYP (CIN to COUT) ps, max
75 Power Consumption Power Basics Quiescent (Static) Current Dynamic CurrentPer logic moduleClock tree
76 Power - Basics Power = Voltage * current = V i Voltage is constant Current = Static + DynamicStatic current: leakage, pullup resistors, DC loadsDynamic Power = kv2fk: constant often referred to as CEQf: frequency
78 Device (Array) Quiescent Current1 Device Voltage Typical Spec LevelType (V) ICC (mA) ICCMAX(mA)A500K <Orion-4KRT <RT1280A <RT14100A <RT54SX <RT54SX32S <UTXQR40xxXLXQVXQVXQVXQVAT60101No DC Loads2Commercial SpecificationXQV600 Lot Data (mA)1lot # min mean max1commercial or industrialworst-case, checking
79 PROM Device Current1 Device Voltage Standby Dynamic @F (MHz) Type (V) ICC (mA) ICCMAX(mA)UT28FUT28F <197A1Specification levels2.5 mA/MHz3BAE Systems (formerly Lockmart) 32kx8 PROM
80 Representative Dynamic Power Numbers A1280/A1280XL Power (mW)F(MHz) Module Input Output Clock Total,440,159, ,879Predicting the Power Dissipation of Actel FPGAsActel Corp, 1996
105 FRAM Memory Functionality Loss During Heavy Ion Test Strip chart of FM1608 (research fab) current during heavy ion irradiation. The device lost functionality during the test while the current decreased from it's normal dynamic levels of approximately 6.3 mA to it's quiescent value, near zero. The device recovered functionally and operated normally throughout the latter part of the test. This effect was seen at least three times during the limited testing of this device.