1. Sungho Kang Yonsei University
Logic Simulation
Sungho Kang
Yonsei University

2. Outline Introduction Simulation Level Delay Models Signal Models
Evaluation
Introduction
Simulation Level
Delay Models
Signal Models
Hazard Detection
Simulation Techniques
Evaluation
Scheduling
Cycle-Based Simulation
Model Generation

3. Digital Simulation
Introduction
Digital simulation is the technique of predicting the behavior of a digital system under failure by a computer program that models the target system
The closer model is to the actual system, the more accurate the simulation
Advantages over physical simulation
Analysis and data collection may begin as soon as the digital system is designed
Diagnostic tests may be developed earlier in the design phase of the system
Manual intervention is not required to produce and record fault responses
Digital simulation may be used for systems of any technology and packaging and many failure mechanisms
Digital simulation can provide additional maintainability information on a proposed design other than the level of fault detection and diagnosis

4. Simulation Process
Introduction

5. Role of Simulation in Design Automation
Introduction

6. Simulation Levels System Level Behavioral Level
Register Transfer Level
Structural Level
Functional Level
Logic Level
Gate Level
Switch Level
Circuit Level
Mixed Level

7. Timing Models Zero Delay Unit Delay Nominal Delay Rise Fall Delay
Delay Models
Zero Delay
Unit Delay
Nominal Delay
Rise Fall Delay
Min-Max Delay
Inertial Delay

8. Zero Delay
Delay Models
Zero delay simulators assume that the propagation time through all devices is zero
Essentially then, a zero delay simulator simply evaluates Boolean equations in order to determine the output of the digital system being simulated
Normally this requires that the logic network be leveled in order to insure the proper hierarchy of evaluation in the Boolean expression
Also feedback loops have to be identified and broken

9. Unit Delay
Delay Models
Unit delay simulators assume that the propagation time is non-zero and is the same for all devices
Since there is a finite delay associated with each device, the model permits limited race and hazard analysis to be performed
This model is applicable to combinational networks which have logic elements with similar delay characteristics
However results must be interpreted carefully to determine if they are representative of the real network

10. Nominal Delay
Delay Models
Nominal delay simulators permit the assignment of a single nominal (average) delay to each element type
This can be more precise if the delay assignments can be made based on the number of device fanins and fanouts

11. Comments on Timing Models
Delay Models
With delay simulation, as with zero delay, the network is expected to stabilize between applications of input patterns
If a network does not stabilize this mean an oscillation has occurred due to some timing problem
Due to weakness of the delay model the oscillations encountered in simulation may not really exist with respect to processing them in the simulator
One procedure which has been used is to set some maximum number of time steps which could occur before the network stabilizes
Once the predetermined number of steps have taken place, simulation is stopped

12. Rise Fall Delay
Delay Models

13. Min-Max Delay
Delay Models
In order to perform very realistic precise delay simulation minimum maximum turn-on delays as well as minimum maximum turn-off delays are needed
Total 4 delay values are associated with each element

14. Comments on Timing Models
Delay Models
Generally speaking, zero and unit delay simulators can be used for logic verification while assignable delay and precise delay simulators are used for design verification in order to detect spikes, hazards and races
Assignable delay and precise delay simulators can also be used for detailed determination of sequential device states, modeling edge-triggered devices, etc
A great deal of information is associated with each device
As a result these simulators are mostly table-driven and more costly in terms of memory and execution time

15. Inertial Delay
Delay Models
For the pure delay, the output waveform is the same as the input waveform except that it is delayed by the delay time tpd
The inertial delay, in addition to delaying the input by the delay period t, outputs only those input values which persist for a time period greater than t
In other words, the inertial delay filters out input pulses which are shorter than the delay time
For both the pure and inertial delays, each input change results in an output change being scheduled to occur after the appropriate delay period
However in the simulation of inertial delay, those scheduled output changes which result from an input change which did not last for at least the delay period are subsequently cancelled, and therefore do not affect the rest of the circuit being simulated

16. Signal Models 2 Value 3 Value 4 Value 5 Value Multi- Value

17. Signal Models
Signal Models
Modeling of values that a continuous signal has during its transition between states, will be considered
It is only when we have both accurate timing models and signal models that an accurate simulation can be achieved in performing critical timing analysis
Usually the choice of particular delay parameters directly affects the number of values used in the simulator
Zero, unit, or nominal delay models can use either two or three values for simulation

18. 2 Value
Signal Models
Minimum requirement to simulate a signal having binary values is assigning 0 and 1 to the 2 states
Drawbacks
Initialization of the logic net to be simulated
Since only two values exist, all signal would be initially set to 0 or 1
Another limitation is that signals cannot be changed to value other than 0 or 1
X's due to spikes, unknowns, etc cannot be generated
Generally if a race condition, spike, or insufficient recovery time is encountered in a simulation using 2 value signal model, the program simply prints a message indicating that it cannot proceed in a deterministic manner

19. 3 Value
Signal Models
Slight variation of the 2 value model is the addition of X value to indicate that it represents an unknown value during transition
The third state value can also be used to represent any input values unspecified or unknown at the beginning of the simulation
This permits the user to easily observe the extent to which the output of a particular gate is propagated through logic
Not only does this facilitate developing diagnostic sequences, but by setting the output of a block of logic to X, it is possible to remove an entire logic block from the simulation

20. 3 Value Evaluation
Signal Models

21. Advantages of 3 Value
Signal Models
Elimination of a reset sequence to initialize the circuit to a known state, since all lines are assumed to initially be in the X state
Enables one to conveniently represent the uncertainty about the state of some lines arising during simulation because of races and hazards
It does not require identification of feedback lines
By avoiding the need for separate specification of the states of 0 and 1 for each element, we greatly reduce the number of different cases which must be simulated

22. X Propagation Problem
Signal Models

23. X Propagation Problem
Signal Models
Incorrect Result

24. How to Solve X Propagation
Signal Models
Simulation
Leveling
Find partition
Include all prime implicants
Normal mode simulation
Partition mode simulation
Simulation with modified values

25. 5 Value Broader spectrum of possible signal values 1 : Logical one
Signal Models
Broader spectrum of possible signal values
1 : Logical one
0 : Logical zero
U : Upward transition
D : Downward transition
E : Potential Error (hazards, undefined conditions)

26. 5 Value
Signal Models

27. 5 Value Evaluation Approximate values for U = 1/4, E = 1/2, D = 3/4
Signal Models
Approximate values for U = 1/4,
E = 1/2, D = 3/4
so, U = 1- U = 1-1/4 = 3/4 =D, etc.

28. Multi-Value
Signal Models
Multiple value simulators are usually those using precise delay times
6 value (0, 1, X, U, D, E)
X : indeterminate
E : potential spike, hazard and race
10 value (0, 1, X, U, D, E, P, N, T, Z)
P : mostly positive
N : mostly negative
Z : high impedance
T : transition to or from Z

29. Compiled Simulation
Simulation Techniques

30. Compiled Simulation LDA B AND Q INV STA E OR A STA F STA Q
Simulation Techniques
LDA B
AND Q
INV
STA E
OR A
STA F
STA Q

31. Levelization
Simulation Techniques

32. Table Driven Simulation
Simulation Techniques
The model of the digital network is formed from the source language input statements by translating the input statements into a data structure representing the network
Advantages
Modifications can be easily done
It can be terminated at any level
Selective Trace
Accuracy
Drawback
Slower in execution time

33. Table Driven Simulation
Simulation Techniques

34. Event Driven Simulation
Simulation Techniques

35. Selective Trace
Simulation Techniques

36. Event Driven Simulation Algorithm
Simulation Techniques
Activated =  /* set of activated gates */
for every event (i, vi) pending at the current time t
if vi  v(i) then
begin /* it is indeed an event */
v(i) = vi /* update value */
for every j on the fanout list of i
begin
update input values of j
add j to Activated
end
for every j  Activated
vj = evaluate ( j )
schedule (j, vj ) for time t+d(j)

37. Time Flow Mechanisms
Scheduling
Next Event
Fixed Time Increment
Hybrid

38. Next Event Events simulated are discarded and storage is allocated
Scheduling
Events simulated are discarded and storage is allocated
New events may be scheduled to occur

39. Fixed Time Increment
Scheduling

40. Time Queue
Scheduling
Showing the circular-list structure of t-loop

41. Hybrid Time Queue
Scheduling

42. Cycle Based Simulation
Cycle-based simulators use algorithms that eliminate unnecessary calculations to achieve huge performance gains in verifying functionality:
Results are only calculated at clock edges.
Inter-phase timing is ignored.
Typically, only two logic states (1s, & 0s) are computed.
By limiting the calculations, cycle-based simulators can provide very large increases in performance over conventional event-driven simulators.

43. Cycle Based Simulation
In comparison, event-driven simulator methods sacrifice performance for rich functionality: every active signal is calculated for every device it propagates through during a clock cycle.
Full event-driven simulators support:
4 to 28 states
simulation of behavioral HDL, RTL, gate, and transistor representations
full timing calculations for all devices
the full HDL standard.
Cycle-based simulators only focus on the functionality of the design and therefore can highly optimize the calculations for that purpose.

44. Cycle Based Simulation