1. Lecture 15 PicoBlaze I/O & Interrupt Interface
ECE 448 – FPGA and ASIC Design with VHDL

2. ECE 448 – FPGA and ASIC Design with VHDL
Required reading
P. Chu, FPGA Prototyping by VHDL Examples
Chapter 16, PicoBlaze I/O Interface
Chapter 17, PicoBlaze Interrupt Interface
ECE 448 – FPGA and ASIC Design with VHDL

3. Syntax and Terminology
Syntax Example Definition sX KK
PORT(KK)
PORT((sX))
RAM(KK) s7 ab
PORT(2)
PORT((s1))
RAM(4)
Value at register 7
Value ab (in hex)
Input value from port 2
Input value from the port specified by register s1
Value from the RAM location 4

4. Addressing modes Immediate mode SUB s7, 07 s7 – 07  s7 ADDCY s2, 08
s C  s2
Immediate mode
SUB s7, 07
ADDCY s2, 08
Direct mode
ADD sa, sf
INPUT s5, 2a
sa + sf  sa
PORT(2a)  s5
Indirect mode
STORE s3, (sa)
INPUT s9, (s2)
s3  RAM((sa))
PORT((s2))  s9

5. Output Decoding of Four Output Registers
ECE 448 – FPGA and ASIC Design with VHDL

6. − − − − Output Instructions C Z OUTPUT sX, KK DIR PORT(KK) <= sX
OUTPUT sX, (sY)
PORT((sY)) <= sX
− −
DIR
IND
− −

7. Timing Diagram of an Output Instruction
ECE 448 – FPGA and ASIC Design with VHDL

8. Truth Table of a Decoding Circuit
ECE 448 – FPGA and ASIC Design with VHDL

9. − − − − Input Instructions C Z INPUT sX, KK DIR sX <= PORT(KK)
INPUT sX, (sY)
sX <= PORT((sY))
− −
DIR
IND
− −

10. Block Diagram of Four Continuous-Access Ports
ECE 448 – FPGA and ASIC Design with VHDL

11. Timing Diagram of an Input Instruction
ECE 448 – FPGA and ASIC Design with VHDL

12. Block Diagram of Four Single-Access Ports
ECE 448 – FPGA and ASIC Design with VHDL

13. ECE 448 – FPGA and ASIC Design with VHDL
FIFO Interface
clk
rst
clk
rst
FIFO
din
dout 8 8
full
empty
write
read
ECE 448 – FPGA and ASIC Design with VHDL

14. Operation of the “Standard” FIFOB C D
−−−−−
ECE 448 – FPGA and ASIC Design with VHDL

15. Operation of the First-Word Fall-Through FIFO
ECE 448 – FPGA and ASIC Design with VHDL

16. ECE 448 – FPGA and ASIC Design with VHDL

17. Timing Diagram of an Input Instruction
ECE 448 – FPGA and ASIC Design with VHDL

18. ECE 448 – FPGA and ASIC Design with VHDL
Interrupt Flow
ECE 448 – FPGA and ASIC Design with VHDL

19. Timing Diagram of an Interrupt Event
ECE 448 – FPGA and ASIC Design with VHDL

20. ECE 448 – FPGA and ASIC Design with VHDL

21. Interrupt Related Instructions
RETURNI ENABLE
PC <= STACK[TOS] ; TOS <= TOS – 1;
I <= 1; C<= PRESERVED C; Z<= PRESERVED Z
RETURNI DISABLE
I <= 0; C<= PRESERVED C; Z<= PRESERVED Z
ENABLE INTERRUPT
I <=1;
DISABLE INTERRUPT
I <=0;

22. Interrupt Interface with a Single Event
ECE 448 – FPGA and ASIC Design with VHDL

23. Interrupt Interface with Two Requests
ECE 448 – FPGA and ASIC Design with VHDL