1. Levels in Processor Design
Circuit design
Keywords: transistors, wires etc.Results in gates, flip-flops etc.
Logical design
Putting gates (AND, NAND, …) and flip-flops together to build basic blocks such as registers, ALU’s etc (cf. CSE 370)
Register transfer
Describes execution of instructions by showing data flow between the basic blocks
Processor description (the ISA)
System description
Includes memory hierarchy, I/O, multiprocessing etc
12/31/2018
CSE378 Single cycle
implementation.

2. Register transfer level
Two types of components (cf. CSE 370)
Combinational : the output is a function of the input (e.g., adder)
Sequential: state is remembered (e.g., register)
12/31/2018
CSE378 Single cycle
implementation.

3. Synchronous design Use of a periodic clock
edge-triggered clocking determines when signals can be read and when the output of circuits is stable
Values in storage elements can be updated only at clock edges
Clock tells when events can occur, e.g., when signals sent by control unit are obeyed in the ALU
Note: the same storage element can be read/written in the same cycle
Stor. Elem 1
Stor. Elem 2
Comb.logic
Clock cycle
12/31/2018
CSE378 Single cycle
implementation.

4. Logic may need several cycles to propagate values
Stor. Elem 1
Stor. Elem 2
Comb.logic
Write signal
Write signal
Logic may need several cycles to propagate values
12/31/2018
CSE378 Single cycle
implementation.

5. Processor design: data path and control unit
CPU
Combinational
Memory hierarchy
control
ALU PC
Registers
state
Sequential
Memory bus
Data path
12/31/2018
CSE378 Single cycle
implementation.

6. Processor design Data path Control unit Memory hierarchy
How does data flows between various basic blocks
What operations can be performed when data flows
What can be done in one clock cycle
Control unit
Sends signals to data path elements
Tells what data to move, where to move it, what operations are to be performed
Memory hierarchy
Holds program and data
12/31/2018
CSE378 Single cycle
implementation.

7. Data path basic building blocks. Storage elements
Basic building block (at the RT level) is a register
In our mini-MIPS implementation registers will be 32-bits
A register can be read or written
Input bus
Register
Write enable signal
Output bus
12/31/2018
CSE378 Single cycle
implementation.

8. Register file
Array of registers (32 for the integer registers in MIPS)
ISA tells us that we should be able to:
read 2 registers, write one register in a given instruction (at this point we want one instruction per cycle)
Register file needs to know which registers to read/write
Read register number bus 0
Write register number
Read register number bus 1
Write enable
Read data output bus 0
Write data input bus
Register file
Read data output bus 1
12/31/2018
CSE378 Single cycle
implementation.

9. Memory Conceptually, like register file but much larger
Can only read one location or write to one location per cycle
Read memory address
Write memory address
Read control signal
Write enable
Memory
Read data bus
Write data bus
12/31/2018
CSE378 Single cycle
implementation.

10. Combinational elements
Multiplexor (Mux): selects the value of one of its inputs to be routed to the output
Input busses
Mux
Select control signal
Demultiplexor (selector): routes its input to one of its outputs
Output bus
Output busses
Sel
Select control signal
Input bus
12/31/2018
CSE378 Single cycle
implementation.

11. Arithmetic and Logic Unit (ALU - combinational)
Computes (arithmetic or logical operation) output from its two inputs
Zero result bit
Input bus 0
ALU
Output bus
Input bus 1
ALU control (opcode/function)
12/31/2018
CSE378 Single cycle
implementation.

12. Putting basic blocks together (skeleton of data path for arith/logical operations)
Zero result bit
Read register number bus 0
Write register number
Read register number bus 1
Write enable
Read data 0
ALU
Register file
Read data 1
ALU control (opcode/function)
Write data input bus
12/31/2018
CSE378 Single cycle
implementation.

13. Introducing instruction fetch
Zero result bit
Read Reg #0
Read Reg #1
Write Reg #
Read data 0
ALU
Reg. File
Read data 1
ALU control (opcode/function)
Write data
Instruction address
Instr. memory PC
12/31/2018
CSE378 Single cycle
implementation.

14. PC has to be incremented (assume no branch)4
ALU
Instruction address
Instruction
Instr. memory PC
12/31/2018
CSE378 Single cycle
implementation.

15. Load-Store instructions
Read enable
Instruction
Read data 0
Read Reg #0
Read Reg #1
Write Reg #
ALU
Data memory
R/W address
Reg. File
32-bit
“store” data
Sign.
ext
16-bit offset
Write enable
Data from “load”
12/31/2018
CSE378 Single cycle
implementation.

16. Data path for straight code(reg-reg,imm,load/store)
Read enable
Instruction
Read data 0
Read Reg #0
Read Reg #1
Write Reg #
ALU
Read data 1
Data memory
R/W address
Reg. File
32-bit
Sign.
ext
“store” data
16-bit offset
Write enable
Data for result register
Mux
12/31/2018
CSE378 Single cycle
implementation.

17. Branch data path ALU 4 ALU Inst. memory PC Sftl 2 32-bit Instruction
Sign.ext
12/31/2018
CSE378 Single cycle
implementation.