1. Design Methodology for IC Manufacturability Based on Regular Logic-Bricks
V. Kheterpal, V. Rovner, T.G. Hersan, D. Motiani,
Y. Takegawa, A.J. Strojwas, L. Pileggi

2. IC Design and Manufacturing Challenges
Light source wave length
Tech node
year
[nm]
ArF
X-ray
KrF
(F2)
Significant challenges due to sub-wavelength lithography
CD is proportional to the wavelength of light, and inversely proportional to the Numerical Aperture (NA) of the lens
Lambda has not been scaling
NA has been increased with immersion, but at the expense of depth-of-focus
Resolution enhancement techniques (RETs) reduce k1

3. Regularity By Design
Resolution Enhancement Techniques (RETs) are time-consuming and difficult to optimize for large process windows
Defocus, Illumination conditions, Pattern neighborhood
Conventional design rules are insufficient to guarantee design’s adherence to RETs
Increasing need for more geometry regularity by design
Sensitive to grow
due to defocus
Sensitive to shrink
Sensitive to
exposure variation
resist effects

4. Regular Geometry Fabric
Regularity By Design
Constraining number of geometry primitives implies more regular FEOL circuits and BEOL metal patterns
FPGAs and memories are the first products ported to a new technology due to the (macro) regularity
Create manufacturable block (CLB) or cell by silicon characterization and simulation trial-and-error
Neighborhood is other similar cells, so it can be replicated to create manufacturable arrays
Regular Geometry Fabric
Regular Circuits
constraints

5. Measuring Regularity Grid of CD shapes with 500nm pitch
Highest peak at 2“Hz”
2-D FFT plots of poly-Si patterns

6. Memory Array Macro-regularity due to repeated bit-cells
Spread of the impulses due to irregularity within bit-cells
2-D FFT plots of poly-Si patterns

7. ASIC Standard Cells
Std cells have no significant micro or macro regularity
Increasingly challenging to precharacterize all layout dependencies and precisely print all geometry patterns with a single optical setup
2-D FFT plots of poly-Si patterns

8. Regular Layout Fabric Single orientation of CD lines Fixed poly pitch
Easy resolution of phase conflicts
Fixed poly pitch
Process optimized for single pitch (or its multiple)
Eliminate existence of illegal pitches
Disallow minimum width devices
Decrease number of active corners
Easier OPC of active layer
Contacts on the grid
Chose P of 500nm for our 90nm experiments
Very conservative – adds area and parasitic penalty P
mms mw
mce

9. Macro Regularity Brick 1 Brick 2 Identical boundaries
Guarantee seamless boundaries across abutted cells (Bricks)
Well pre-characterized region of influence r r r
Brick 1
Brick 2
Region of influence
Identical boundaries

10. Regular Logic Bricks
Map a simple set of logic primitives onto regular fabric patterns to form logic bricks
Mixed PTL-CMOS logic style
Fast PTL Muxes embedded within the bricks
Buffered brick outputs
Performs multiple boolean functions using configurable vias

11. Brick Generation
Reduction of a set of Logic blocks into a smaller set of Via-configurable blocks
Merging blocks
Efficiently implement 2 blocks within one via-configurable block
Graph Matching
Grouping N logic blocks into a smaller number of via-configurable blocks
Area optimization

12. Computing Configuration Efficiency
Build bipartite graphs:
Weights represent similarity in neighborhood
Perform maximum cost graph matching to derive optimal via- configurable block

13. Brick Derivation Example
Merging logic groups into via-configurable bricks
The fewer unique bricks, the better the macro regularity
But too few bricks produce poor area and performance
Merged
Iteration 1
Iteration 2

14. Brick Generation – Area Tradeoff
Little area benefit for using more than 10 unique bricks
Few unique bricks allows for macro regularity and silicon validation analogous to CLBs and bit cells
Trade-off between number of geometry patterns and area/performance

15. Initial Experiments Derive a generic (3-input functions) Brick library
Choose implementations of 3-input functions using the logic primitives (MUXs, NANDs)
Reduce the above set of logic-blocks into a smaller set of via-configurable Bricks using our Brick derivation methodology
Configurable to any 3-input function (multiple outputs, etc.)
Identical physical footprints and INV boundaries
500nm poly pitch, M1 and contacts on grid (15-20% area penalty)
Used fixed-size combinations of NAND2s, NAND3s, and Muxes
Used discrete set of variable size INVs
Can resize brick-boundary INVs w/o disturbing regularity
Restrict routing upto M4

16. Generic, Configurable Brick Library
5 Generic bricks (all 3 input functions) + D Flip-flop
Fixed-width

17. Mapping RTLs to Brick Libraries
Characterize library of brick primitives based on expected within-brick performance
Perform logic synthesis from RTL to the library of brick-primitives
Perform physical synthesis & placement of brick-primitives
Pack brick-primitives into bricks
Rebuffer (custom INV sizing without disturbing regularity) and perform detailed routing

18. Generic Brick Library: Area
ASIC not on grid (15-20% area advantage over equivalent gridded brick)
Brick implementation is competitive with ASIC on-grid
Efficient in performing complex 3-input functions such as in the Nswitch
Area penalty for designs requiring richer set of logic primitives (e.g. datapaths)

19. Generic Brick Library: Performance
ASIC Library with full sizing capability
Immediate advantages in designs (e.g. Dspcore & Nswitch) which have complex 3-input functions
Needs specific brick library for datapath designs (e.g. Koggestone) which have simpler brick cells

20. Regularity of Generic Bricks
Array of Bricks regularity comparable to memory array regularity
Can push brick design rules as is done for high density bitcells

21. Summary & Future Work
Proposed a new design flow for ICs based on Regular Logic-Bricks
Showed that a small number of configurable logic-blocks is sufficient to have an efficient implementation of a design
Very competitive results given the on-grid restrictive design rules for the Bricks
Future work
Explore additional gates
in the primitive set
Application specific Bricks