1. Multiplexer Implementation of Digital Logic Functions
Dr. Bhanu Bhaskara
NMR Engineering College
Hyderabad

2. FPGA Architecture

3. Xilinx CLB

4. Xilinx Spartan FPGA

5. Digital Logic Functions
Combinational Logic
Implemented using Gates
NAND Implementations
Sequential Logic
Consists of Flip Flops
Inside - NAND gates
NAND gate using MUX?

6. MUX with NAND
F = (p.q)'

7. 2:1 Mux
F = s’ p + s q 1 p q s F

8. 2:1 Mux G = a’ + b’ G = a’ + a b’ G = a’.1 + a. b’ F = s’ p + s q 1 p1 p q s F
G = a’ + b’
G = a’ + a b’
G = a’ a. b’
F = s’ p + s q 1 G b’ 1 a

9. Output? U a 1 1 W C’ 1 1 V b’ D E

10. Configurable? U ? ? 1 W ? 1 1 V ? ? ? ?

11. See you Guys in the next class!