1. The Interconnect, Control, and Instruction Decoding
CS/COE 0447 (term 2181)
Jarrett Billingsley

2. Class announcements OMETs are open until 12/10!!!!
We are at 21/67 = 31%!
That means 30 more responses needed for cookies 🍪🍪🍪🍪
11/28/2017
CS/COE 0447 term 2181

3. The Interconnect
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CS/COE 0447 term 2181

4. Gotta keep em separated interconnected
We've got pieces of a CPU, but they don't operate in isolation.
We gotta hook em together. But which parts hook to which?
Well… let's look at the ISA. The instructions in the ISA tell you what has to connect to what.
PC that can branch and jump
Register File
ALU
Data Memory
Instruction Memory
11/28/2017
CS/COE 0447 term 2181

5. Slowly coming together
If we look at all the different instructions we want to support, we'll start to get an idea of what data goes where.
sub v0, t0, t1
sw s0, 4(t3)
Register File
ALU t0 t1 v0 -
Data Memory
Register File
ALU s0 t3 + 4
Data
Address
jal move_ball
ALU?
Register File PC + 4 ra
address of move_ball
How do we make all these different things happen with one set of hardware…?
11/28/2017
CS/COE 0447 term 2181

6. PC to the left of me, ALU to the right, here I am
The interconnect lets the CPU parts combine in many ways.
It's like the CPU's "circulatory system" – it moves data around.
Register File
Data Memory PC
jal
stores jr
loads
Instruction Memory
li (immediate)
add, sub, etc.
ALU
addi, ori etc.
It's starting to take shape…
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CS/COE 0447 term 2181

7. instruction immediates
Conjunction junction
The interconnect makes choices about which things go where.
data from memory
ALU results
instruction immediates
saved PC for jal
Only one of these is written to the register file.
Register File
So how do we choooooose which thing to write?
Now we have a select pin. This is a control signal!
RegDataSrc 2
There will be several MUXes in the interconnect, and each needs a control signal.
The book calls this "MemToReg" which is a terrible name and is inconsistent with the rest of the control signal names
11/28/2017
CS/COE 0447 term 2181

8. Two kinds of control signals
First there are the selects.
These go into the select pins of muxes, demuxes, or decoders.
They can be any number of bits.
Then there are the write enables.
These tell registers and memory when to store data.
They're Booleans - 0 or 1.
Register File
RegWrite rd rs 3
MemWrite
Data Memory
11/28/2017
CS/COE 0447 term 2181

9. Interconnected (MIPS, not µMIPS)
If we want to make a suuuuper simple version of MIPS, we can connect the pieces together into a datapath like this.
Data
Data Memory
(This version doesn't support li and jal, but that's fiiiine)
RegWrite
MemWrite rd
Register File
Address rs
How can we use this to implement add? sub? addi? lw? sw?
ALU rt
RegDataSrc
ALUOp
ALUSrc
But now we need to, uh, control the control signals.
imm field
11/28/2017
CS/COE 0447 term 2181

10. A little tangent: Operand Fetch (OF)
Operand Fetch is a phase of instruction execution you might see.
It's the step before EX: fetching the values to be operated on.
In MIPS (and µMIPS), OF is super simple:
This is by design: load-store architectures have very simple operand fetch phases.
Register File
imm field
ALU
Compare that to x86, a CISC:
inc [eax + ecx*4 + 12]
This says, "multiply ecx by 4, add it to eax and 12, load a word from that address, add 1 to it, and store the word back into memory"
Here it is!
The bold stuff is the OF phase. Doesn't it sound fun?
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CS/COE 0447 term 2181

11. The Control
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CS/COE 0447 term 2181

12. 👀 Feeling nervous Control sub v0, t0, t1 Data Memory
The control is what sets the write enables and selects to the appropriate values to make each instruction happen.
It's like the CPU's brain and nervous system.
c'mon you lazy bums
Control
It does this by reading the instructions.
Register File
awwwww we don't wannaaaa
sub v0, t0, t1 👀
Data Memory
Register file, read t0 and t1, and write to v0. ALU, do subtraction. Interconnect, route the data from the two registers into the ALU and from the ALU into the register file. Data memory, you get to take a break.
ALU
yissssss
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CS/COE 0447 term 2181

13. Gotta write it down sw s0, (t0) add t0, t1, t2 jal func1
Write enables are kind of the basis of "things happening in a CPU."
Almost every instruction writes something somewhere!
add t0, t1, t2
sw s0, (t0)
Writes to memory
Writes to t0
jal func1
beq s0, 10, end
Might write to the PC
Writes to the PC and ra!
If an instruction doesn't write anything, it's a no-op (nop).
(Nothing changed? Then it's like the instruction never happened.)
What changes when a conditional branch isn't taken?
11/28/2017
CS/COE 0447 term 2181

14. + The control hardware PC Control Instruction Memory
We connected the datapath together; now for the control bits. PC
immediate (jump target) 4
PCSrc + rt rd
PCSrc rs
immediate
Control
Instruction goes in…
Instruction Memory
Address goes in…
…control signals come out.
…instruction comes out.
Somehow.
ALUSrc
RegWrite
ALUOp
RegDataSrc
MemWrite
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CS/COE 0447 term 2181

15. Instruction Decoding
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CS/COE 0447 term 2181

16. "Do everything at once, but use only what you need."
Pull 'n' peel
The first step is to split the encoded instruction up.
But which instruction format is it? Actually, it doesn't matter.
31-26
opcode R 31 26 25 21 20 16 15 11 10 6 5
opcode rs rt rd
shamt
funct 32
instruction
25-21 rs
20-16 rt I 31 26 25 21 20 16 15
opcode rs rt
immediate
15-11 rd 31 26 25
opcode
target J
10-6
shamt
5-0
funct
"Do everything at once, but use only what you need."
15-0
immediate
25-0
target
11/28/2017
CS/COE 0447 term 2181

17. No, really, it's fine, don't worry about it
Suppose the encoded instruction was addi s0, s0, -1. 31 26 25 21 20 16 15
opcode rs rt
immediate op rs rt rd
shamt
funct
imm
target 32
0x08
Put it through the splitter and…
0x10
addi is an I-type instruction.
0x10
opcode, rs, rt, and immediate will be used.
addi s0,s0,-1
0x1F
0x2210FFFF
0x1F
The rest are bogus and will be ignored. See? It's fiiiiiine
…out come a bunch of values.
0x3F
0xFFFF
0x210FFFF
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CS/COE 0447 term 2181

18. Making the control work
The control is a boolean function that takes the instruction opcode as its input and outputs the control signals.
In other words, it's a big fat truth table.
I really would not recommend making your control unit like this.
opcode
PCSrc
RegDataSrc
RegWrite
ALUOp …
000000 00
000
000001 01 1
110
000010
010
000011
011
000100 11
000101 10
It's time-consuming, confusing, hard to debug, and hard to change.
You will go insane.
I just made up these numbers. Please don't try to use them.
11/28/2017
CS/COE 0447 term 2181

19. A more approachable approach
Here's a great use for a decoder: decoding. (huh.)
opcode
<r-type>
Exactly one of these will be on at a time.
<uhh random crap> j
jal
Now it's just a matter of coming up with the logic for each of the control signals.
beq
bne
blez
For that, it's good to focus on one control signal at a time.
bgtz
addi
addiu
slti
sltiu
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CS/COE 0447 term 2181

20. <the sound a seal makes>
Let's say we want to come up with the MemWrite control signal.
Which instructions write to memory? sw sh
MemWrite sb
Pretty straightforward, huh?
What about multi-bit control signals, like your ALU operation?
11/28/2017
CS/COE 0447 term 2181