1. ESD Test Methodology
Vdd
Vss
+V / - V
I/O

2. Function Test ESD Stress Zapping Function Test
Chip Level ESD Stress Zapping Test … General
Function Test
ESD Stress Zapping
Function Test
JEDEC Standards
Most chip manufacturers officially comply with the general procedure defined by the JEDEC Standards.
In reality, the ESD stress zapping procedure and the contents of the function test are still different, company by company.
ESD Stress Model : HBM Model, MM Model, CDM Model
Pin Combination Mode : Vss Reference Mode, Vdd Reference Mode and Pin-to-Pin Mode
( In principle, all the pins are required to be stressed against every other pin in turn, which is practically unfeasible.
Thus a reasonable judgment has to be made regarding pin-to-pin combination which can reflect real-world ESD stress fluxing situation. )
Referencing Method : Grouping Methods, Isolation Methods, Separation Methods
Injection Polarity : Three Positve and Three Negative Pulses with Pulse Interval 1sec.
ESD Pass Level : Worst Case ESD Performance.
Test Sample Number : At Least 3 Samples in Each Model, Level, and Mode

3. Vdd Reference Mode Vdd Reference Mode
Chip Level ESD Stress Zapping Test … Combination of Zapping Pins
Vdd Reference Mode
Vdd Reference Mode
Vdd
Vss
+V / - V
I/O
Vdd
Vss
+V / - V
I/O
Vss : Grounded
Others pins ( Vdd & I/O) are zapped, pin by pin.
Vdd : Grounded
Others pins ( Vss & I/O) are zapped, pin by pin.
The ‘Vss Reference Mode’ and the ‘Vdd Reference Mode’ are commonly adopted test methodology for HBM and MM type ESD stress zapping.

4. Chip Level ESD Stress Zapping Test … Combination of Zapping Pins
Pin-to-Pin Mode
Vdd
Vss
+V / - V
I/O
Vss, Vdd : Floating
All other I/O pins are shorted and connected to the ground except for the zapped pin. Zap all the I/O pins, pin by pin.
The ‘Pin-to-Pin Mode’ is sometimes adopted as a test methodology for HBM and MM type ESD stress zapping.

5. Chip Level ESD Stress Zapping Test … CDM Stress Zapping Methodology
Charging
Draining-Out ( Pin-to-Pin Mode )
Vdd
I/O
Vss
Direct Contact Charging or Field Induced Charging
Each Pin ( Vdd, Vss & I/O) is grounded, pin by pin.
The device under test is first charged either by strong electric field ( Field Induced CDM ) or by direct contact with biased electrode ( Socket CDM ).
Once the device is charged, then each pin is grounded and discharged, pin by pin.

6. Chip Level ESD Stress Zapping Test … Reference Grouping Methodology
Ground Reference 1
Power Reference 1
Power Reference 2
IO Pad
NM_LV
NM_MV
NM_HV
ND_HV
PD_HV
Grouping
Isolation
Separation
VGH
15.0V
VGH
15.0V
VGH
15.0V
AVdd
5.0V
AVdd
5.0V
AVdd
5.0V
Vdd
3.3V
Vdd
3.3V
Vdd
3.3V
VCC
1.8V
VCC
1.8V
VCC
1.8V
Vss
0.0V
Vss
0.0V
Vss
0.0V
VCL
-5.0V
VCL
-5.0V
VCL
-5.0V
VGL
-10.0V
VGL
-10.0V
VGL
-10.0V
Internal
External
Internal
External
Internal
External
Reference : Both Internal & External
All References are Shorted.
Reference : External Only
All References are Shorted.
Reference : External Only
References only with Same Potential are shorted.

7. Chip Level ESD Stress Zapping Test … Example of ESD Stress Zapping Test Sheet