1. SCR-Stacking Structure With High Holding Voltage For I/O And Power Clamp
ICECE 2015
Hyun young Kim, Chung Kwang Lee, Han Hee Cho, Sang Woon Cho
Yong Seo Koo(Corresponding author)
Department of Electronics and Electrical Engineering
Dankook University
Gyeonggi-do, Republic of Korea /

2. Contents
Introduction
SCR-based ESD Protection Circuit
3. Conclusions

3. 1. Introduction [ESD Phenomenon and Basic Design of ESD Clamp]
I/O Clamp for ESD Protection circuits
Power Clamp for ESD Protection circuits
Discharge event due to tribo-electrically generated charges.
ESD is a high-current (~Amps) and short-duration (~ns) stress event.
ESD events are classified in three main categories. (HBM, MM, CDM)
ESD Protection Network turn on only when an ESD pulse is detected and turn off during normal operations.

4. 1. Introduction [Conventional SCR]
< Cross section of the Conventional SCR circuits
and equivalent circuits>
SCR has been considered as an on-chip ESD protection circuit
because of its high current capability and high failure current.
High trigger voltage (~20V) ▶Oxide breakdown
Low holding voltage (1~2V) ▶Latch-up
As technology scale down, the value of trigger voltage(VT1)
should be less than the oxide breakdown voltage.
In order to avoid the latch-up during normal operation condition,
holding voltage should be greater than operating voltage(VDD)
I/O Clamp
Power Clamp

5. 2. SCR-based ESD Protection Circuit
[Proposed ESD protection circuit]
Additional
BJT operation
I/O and power clamp
< Cross section of the proposed ESD protection circuits
and equivalent circuits>
< Application circuit >
Proposed ESD protection circuit
Conventional SCR
Trigger Voltage(Vt)[V]
20.5 26
Holding Voltage(Vh)[V]
3.3
1.5
Low Trigger
Voltage
High Holding
The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD Protection circuit.
< Simulation results>

6. 2. SCR-based ESD Protection Circuit
[Simulation Results]
< Result Table>
D1 Variation
D2 Variation
D1 Variation[um] 5
7.5 10
Holding Voltage [V]
3.3
4.7
5.6
Trigger Voltage [V]
20.5
21.8
22.9
D2 Variation[um] 1 2 3
Holding Voltage [V]
3.3
4.8
7.9
Trigger Voltage [V]
20.5
21.8
23.8
D3 Variation[um] 1 3 5
Holding Voltage [V]
3.3
4.5
6.5
Trigger Voltage [V]
20.5
22.1
23.1
D3 Variation
Stack Variation
Stack Variation[number] 1 2 3
Holding Voltage [V]
3.3
6.8
10.5
Trigger Voltage [V]
20.5 41 58

7. 3. Conclusions
This paper proposed SCR-based ESD protection circuit with high holding voltage for I/O and Power Clamp.
In comparison to conventional SCR, these proposed circuit have low trigger voltage and high holding voltage.
The holding voltage for the single proposed SCR-based circuit has been increased from 3.3V to maximum 7.9V as a design parameters(D1,D2,D3) increases.
The holding voltage of each stack structure can be identified as 3.3V, 6.8V and 10.5V respectively.
The proposed SCR-based ESD protection circuit has latch-up immunity characteristics due to the high holding voltage and the high robustness is expected to improve reliabilty of integrated devices more.