Presentation is loading. Please wait.

Presentation is loading. Please wait.

RTAX-S Qualification and Reliability Data September 7-9, 2005 2005 MAPLD International Conference Minal Sawant Ravi Pragasam Solomon Wolday Ken O’Neill.

Published byCalvin Richards Modified over 8 years ago

Similar presentations

Presentation on theme: "RTAX-S Qualification and Reliability Data September 7-9, 2005 2005 MAPLD International Conference Minal Sawant Ravi Pragasam Solomon Wolday Ken O’Neill."— Presentation transcript:

1 RTAX-S Qualification and Reliability Data September 7-9, 2005 2005 MAPLD International Conference Minal Sawant Ravi Pragasam Solomon Wolday Ken O’Neill

2 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 2 Outline  Design Overview  MIL-STD-883B  Enhanced Antifuse Qualification (EAQ)  Sample Size and Test Sequence  Results  MIL-STD-883B  Enhanced Antifuse Qualification (EAQ)  Enhanced Lot Acceptance (ELA)  Plan  Results Terminology: EAQ = ELA (both processes use the same design) Group C = High Temperature Operating Life (HTOL) = Dynamic Programmed Burn In (DPBI)

3 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 3 Design Overview  MIL-STD-883B  Uses the QBI (Qualification Burn In) design  Goal: Device Feature  Maximum Utilization of logic cells  Test all IO standards  Test all macro offering (Carry chain, buffys etc)  Test RAM feature  Test for propagation delay Note: QBI = QCMON  EAQ  Uses the EAQ design  Goal: Antifuse Reliability  Tests all possible antifuse type  Based on NASA style design  Test for delay perceptibility

4 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 4 Top Level  QBI Design  EAQ Design

5 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 5 Delay Paths  QBI includes one small delay chain  EAQ includes 8 delay chains 22 Stages: ~ 36 ns

6 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 6 Design Summary  QBI  I/O’s are configured with all the different combinations of I/O standards, slew and pull-up resistor (I/O standards LVTTL, PCI, and PCIX, LVPECL, and Vref are used)  EAQ (RTAX1000S-CG624)

7 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 7 Antifuse Utilization

8 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 8 Sample Size  QBI :  129 equivalent RTAX2000S-CQ352B devices used at 125°C  Additional 78 devices of RTAX1000S-CQ352B used for LTOL (Low Temperature Operating Life) experiment at -55°C  EAQ :  300 devices of RTAX1000S-CG624 used

9 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 9 Test Sequence  QBI : HTOL  QBI : LTOL  EAQ : AXS1  EAQ : ASX2

10 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 10 QBI Summary  QBI  For RTAX2000S (87 units) = 84 + 3 spares  For RTAX1000S (98 units) = 90 + 8 spares  7 failures were observed during the HTOL and LTOL tests

11 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 11 QBI FA Investigation & Conclusions  All the 7 failures* observed from the (QBI) devices indicated identical failure signature due to equipment induced ESD  Physical Failure analysis indicated damage to the ESD circuit  Duplication of failure mode with MM testing indicated identical failure signature  ESD zap is due to the charge buildup on the CQ352 socket lid  This charge does not exist on the CG624 package  Thus no failures observed in the EAQ experiment  No additional failures due to ESD have been observed since the use of ESD friendly and staticide treated socket lids  De-processing of a second failed device showed the same failure signature  RTAXS Passed ESD at 2000 V HBM  RTAXS Passed ESD at 250 V MM *Failure analysis report available upon request

12 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 12 EAQ Summary  EAQ  9 failures were observed during the HTOL and LTOL tests  8 Failures had identical failure signature  1* (HTOL after 1000 hrs) unit has a different failure signature  Failure Analysis under progress  Antifuse has been eliminated as a potential cause  No Antifuse failures observed  EAQ experiment will be continued for an extra 1000 hours of HTOL on a sample size of 120 units from above lot  Results expected by Mid October 2005

13 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 13 EAQ FA Investigation Conclusions  Analysis and testing showed that all 8 failures* were on the same output pin “AE16”  All 8 devices came from burn-in board locations D1 and D2  Failure analysis indicated that the damage was on the output buffer pull-down transistor  Damage was due to contention problem on the burn-in boards  The -1V on the output, with over 300 mA current, exceeded the absolute worst case condition for extended periods  No additional failures have been observed since the contention was eliminated  AXS1 completed 250 hrs of LTOL and AXS2 completed 1000 hrs of HTOL with no failures  De-processing of a second failed device showed the same failure signature * Failure analysis report available upon request

14 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 14 ELAPlan  Uses the same high perceptive design as EAQ  ELA is the EAQ design used in the production flow of RTAX-S devices  A sample of units will be tested per each wafer lot before shipment  This will qualify the lot for shipment  Units will be programmed to the ELA design  Units will be sent for 168 hours of Burn in at 125°C  100% yield is required to qualify lot for shipment

15 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 15 ELAResults  Results to date – No Antifuse failures  Shipping RTAX-S to Space Flight Applications today

16 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 16 DSCC SMD Application Status  SMD#  Pre-assigned SMD# for RTAX-S are  5962-04219 for RTAX250S  5962-04220 for RTAX1000S  5962-04221 for RTAX2000S  SMD Application  SMDs in draft  Derived from Actel datasheet  Qualification Package in preparation  Qual results, FA reports, with TRB approval minutes  Qual lots attribute sheets, copies of assembly/test/burn-in travelers  Silicon technology summary  with XSEM showing planarized process  Support documents  Submission to DSCC being planned for the end of October 2005  Certification expected by the end of 2005

17 Sawant, Wolday, Pragasam, O’NeillRTAX-S Qualification and Reliability Data MAPLD 2005 - # 1032 17 Conclusion  NO ANTIFUSE FAILURES  More than 650,000 hours of test data available now  MIL-STD-883B Qualification completed successfully  EAQ experiment completed successfully  150 units with 1000 hours of HTOL and 250 hours of LTOL  150 units with 250 hours of LTOL and 1000 hours of HTOL  Shipping RTAX-S to Space Flight Applications today  Both “B” & “E” flows shipping

Download ppt "RTAX-S Qualification and Reliability Data September 7-9, 2005 2005 MAPLD International Conference Minal Sawant Ravi Pragasam Solomon Wolday Ken O’Neill."

Similar presentations

NASA RTSX-SU Test Update May 10 th, 2006 Presented by Daniel Elftmann.

NASA RTSX-SU Test Update May 10 th, 2006 Presented by Daniel Elftmann.
©2006 The Aerospace Corporation Activities Associated With Working With Xilinx to Develop A Space Flow for Virtex Family of FPGA’s Larry Harzstark The.

©2006 The Aerospace Corporation Activities Associated With Working With Xilinx to Develop A Space Flow for Virtex Family of FPGA’s Larry Harzstark The.
Slides based on Kewal Saluja

Slides based on Kewal Saluja
VirtexII 3000 FPGA Dynamic Burn-In Test For Military And Aerospace Applications Sponsored By NASA Electronic Parts and Packaging Program (NEPP) Electronic.

VirtexII 3000 FPGA Dynamic Burn-In Test For Military And Aerospace Applications Sponsored By NASA Electronic Parts and Packaging Program (NEPP) Electronic.
RTSX-S and RTSX-SU Reliability Test Vehicles Daniel K. Elftmann Director Product Engineering Richard Katz Head Grunt Office of Logic Design Igor Kleyner.

RTSX-S and RTSX-SU Reliability Test Vehicles Daniel K. Elftmann Director Product Engineering Richard Katz Head Grunt Office of Logic Design Igor Kleyner.
Centro Astronómico de Yebes Observatorio Astronómico Nacional HIFI CAY 15/04/03SRON (Groningen)1 First Stage Cryogenic IF Amplifier Carmen Diez.

Centro Astronómico de Yebes Observatorio Astronómico Nacional HIFI CAY 15/04/03SRON (Groningen)1 First Stage Cryogenic IF Amplifier Carmen Diez.
Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.

Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.
Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt1 Lecture 19alt I DDQ Testing (Alternative for Lectures 21 and 22) n Definition n Faults detected.

Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt1 Lecture 19alt I DDQ Testing (Alternative for Lectures 21 and 22) n Definition n Faults detected.
Lecture #26 Gate delays, MOS logic

Lecture #26 Gate delays, MOS logic
Introduction to Op Amps

Introduction to Op Amps
Enhanced X-Ray Shielding Device Package Raymond Kuang Randy Sampan September 7 - 9, 2005.

Enhanced X-Ray Shielding Device Package Raymond Kuang Randy Sampan September 7 - 9, 2005.
Chip Carrier Package as an Alternative for Known Good Die

Chip Carrier Package as an Alternative for Known Good Die
Defense and Aerospace Screening Flows Joe Fabula

Defense and Aerospace Screening Flows Joe Fabula
Submission 1003Baranski1 Reliability Studies on Aeroflex’s RadHard ViaLink TM PROM Brian Baranski, Anthony Jordan, and Craig Hafer Aeroflex Colorado Springs.

Submission 1003Baranski1 Reliability Studies on Aeroflex’s RadHard ViaLink TM PROM Brian Baranski, Anthony Jordan, and Craig Hafer Aeroflex Colorado Springs.
SpaceWire Physical Layer Fault Isolation, Barry M Cook (4Links Limited), Wahida Gasti (ESA), Sven Landstroem (ESA) at ISC 2008 1 SpaceWire Physical Layer.

SpaceWire Physical Layer Fault Isolation, Barry M Cook (4Links Limited), Wahida Gasti (ESA), Sven Landstroem (ESA) at ISC SpaceWire Physical Layer.
2005 MAPLD, Paper 240 JJ Wang 1 Total Ionizing Dose Effect on Programmable Input Configurations J. J. Wang, R. Chan, G. Kuganesan, N. Charest, B. Cronquist.

2005 MAPLD, Paper 240 JJ Wang 1 Total Ionizing Dose Effect on Programmable Input Configurations J. J. Wang, R. Chan, G. Kuganesan, N. Charest, B. Cronquist.
Experiences Deploying Xrootd at RAL Chris Brew (RAL)

Experiences Deploying Xrootd at RAL Chris Brew (RAL)
ESD for the Fabless Semiconductor Company Golden Rules of ESD Due Diligence for Third Party Intellectual Property Golden Rules of ESD Due Diligence for.

ESD for the Fabless Semiconductor Company Golden Rules of ESD Due Diligence for Third Party Intellectual Property Golden Rules of ESD Due Diligence for.
1 Delay Estimation Most digital designs have multiple data paths some of which are not critical. The critical path is defined as the path the offers the.

1 Delay Estimation Most digital designs have multiple data paths some of which are not critical. The critical path is defined as the path the offers the.

Similar presentations

Ads by Google