1. Asynchronous Primitives in CML
High-Speed and Low-power VLSI
97.575
Winter 2003
Professor: M. Shams
Prepared by: Masoud Mashhouri

2. Introduction
In this presentation, CML gates and their advantages and disadvantages are discussed.
Also, a summary of a brief description of Asynchronous circuit is presented.
It is the main goal of this project to integrate the CML primitives into Asynchronous circuits.

3. Virtues of CML
Due to less number of PMOS transistors the input capacitance of these gates is lower than conventional CMOS. Therefore the speed is higher.
And,…the area is also much smaller than conventional CMOS.
Switching Noise non-existent, therefore the ground bounce is minimized. This is ideal for High-Frequency Application.

4. Draw-Backs
It has a constant power dissipation due to the continuous current through the current source.
Cascading is difficult due to the low output driving power.

5. CML Basic Elements
[Ref. 2]

6. Modified CML Basic Elements Inverter
Type (1) Inverter
Type (2) Inverter
[Ref. 1]

7. Modified CML Universal Gates
Type (1) Universal Gate
Type (2) Universal Gate
[Ref. 1]

8. Modified CML Basic Elements D-Flip-Flops
Type(1) D-Latch
Type(2) D-Latch

9. Asynchronous Circuit
Asynchronous Circuit have better performance. Among all other advantages, we can list:
No power dissipation when circuit is Idle.
No Clock network
No concern about clock skew
No power dissipation due to a clock network
Noise Immunity
Modularity
Technology Migration is easier in Asynchronous circuits.

10. Asynchronous Circuit Configurations
Four - 
Request
Sender
Receiver
Acknowledge

11. Four -  Timing Diagram Sender Receiver Request Request Acknowledge
Phases
Data
Data
Acknowledge

12. Two - Timing Diagram Sender Receiver Acknowledge Request Request
Phases
Acknowledge
Request
Request
Acknowledge 1
Sender
Receiver
Data

13. Primitives of Asynchronous Circuits
WIRE a b
IWIRE b a
JOIN a c b
MERGE a c M b
MERGE b a c

14. Implementation of “JOIN”: C-Elements (Truth Table)
Input A
Input B
Output
Low
High
Previous
State

15. Implementation of “JOIN”: C-Elements (State Diagram)b
[Ref. 3]

16. C-Elements and Its Implementations (CMOS)-1
Sutherland’s Circuit

17. C-Elements and Its Implementations (CMOS)-2
Martin’s Circuit
Van Berkel’s Circuit
[Ref. 4]

18. Project Schedule April 1-7:Study, Preparation and Preliminary Design.
April 8-19: Final Design,Testing and Simulation.
April 20-28: Project Finalizing and Report preparation.
May 5: Project Final Presentation.

19. Conclusion
In this presentation a brief description of CML and Asynchronous circuits were discussed.
This presentation provides the background for the project at hand.

20. References
1.Kamran Irvani, Farshid Saleh, et. Al “ Clock and Data recovery for 1.25 Gb/s Ethernet Transceiver in 0.35 µm CMOS”.
2.Jason Musicer, M. Eng. Thesis.
3.Maitham Shams, et al, “Asynchronous Circuits”.
4.Maitham Shams, et al, “ A Comparison of CMOS Implementations of an Asynchronous Circuit Primitive: the C-Element”.