1. Interrupts and exceptions

2. Interrupts and exceptions
Exceptions: Result from unexpected situations (from within the CPU)
Interrupts: Result from external events, e.g. keyboard.
Similar effect. Need to:
Save current CPU state
Execute some appropriate set of instructions
Resume normal execution (sometimes)

3. Interrupt and exception
Type of event MIPS terminology From Where ?
Interrupt External I/O device request
Invoke Operation system Internal Exception
From user program
Arithmetic Overflow Internal Exception
Using an undefined
Instruction Internal Exception
Hardware malfunctions Either Exception or interrupt
חובר בספטמבר 2001

4. Handling exceptions Address 40000040: Fixed location of exception
Handling procedure

5. Handling exceptions

6. Exception Handling procedure
Save on the stack all register values and internal CPU state (taken from the most recent pipeline register)
Lookup the value written in the cause register
Call the appropriate exception handling subroutine.
When subroutine returns:
Upload back all the registers and inernal CPU state
Return to execute interrupted program

7. Faults Instruction would be illegal to execute Examples:
Writing to a memory segment marked ‘read-only’
Reading from an unavailable memory segment (on disk)
Executing a ‘privileged’ instruction
Detected before incrementing the PC
The causes of ‘faults’ can often be ‘fixed’
If a ‘problem’ can be remedied, then the CPU can just resume its execution-cycle

8. Error Exceptions
Most error exceptions — divide by zero, invalid operation, illegal memory reference, etc. — translate directly into CPU signals
Exceptions are handled by the operating system. Usually the job is fairly simple: send the appropriate signal to the current process
force_sig(sig_number, current);
That will probably kill the process, but that’s not the concern of the exception handler
One important exception: page fault
An exception can (infrequently) happen in the kernel
die(); // kernel oops

9. Traps
A CPU might have been programmed to automatically switch control to a ‘debugger’ program after it has executed a specific instruction
That type of situation is known as a ‘trap’
It is activated after incrementing the PC

10. Interrupts Motivation:
Utility of a general-purpose computer depends on its ability to interact with I/O devices attached to it (e.g., keyboard, display, disk-drives, network, etc.)
Devices require a prompt response from the CPU when various events occur, even when the CPU is busy running a program
Need a mechanism for a device to “gain CPU’s attention”
Interrupts provide a way doing this

11. Simplified Architecture Diagram
Central
Processing
Unit
Main
Memory
system bus
I/O
device
I/O
device
I/O
device
I/O
device

12. Programmable Interval-Timer
Interrupt Hardware
IRQs
Slave
PIC
(8259)
Master
PIC
(8259)
x86
CPU
Ethernet
INTR
SCSI Disk
Real-Time Clock
Keyboard Controller
Programmable Interval-Timer
I/O devices have (unique or shared) Interrupt Request Lines (IRQs)
IRQs are mapped by special hardware to interrupt vectors, and passed to the CPU
This hardware is called a Programmable Interrupt Controller (PIC)

13. The `Interrupt Controller’
Responsible for telling the CPU when a specific external device wishes to ‘interrupt’
Needs to tell the CPU which one among several devices is the one needing service
PIC translates IRQ to vector
Raises interrupt to CPU
Vector available in register
Waits for ack from CPU
Interrupts can have varying priorities
PIC also needs to prioritize multiple requests
Possible to “mask” (disable) interrupts at PIC or CPU

14. CPU’s ‘fetch-execute’ cycle
User
Program
Fetch instruction at PC ld
add st
mul
sub
bne
jmp … PC
Decode the fetched instruction
Save context
Get INTR ID
Execute the decoded instruction
Lookup ISR
Advance PC to next instruction
Execute ISR
Interrupt?
yes
IRET no

15. Handling interrupts Similar to exception handling, except:
Interrupt information are held in two registers: Interrupt Cause and Interrupt Status
Interrupts have priorities
During execution of handling code for interrupt of level L, only interrupts of level > L can create new interrupt

16. Putting It All Together
Memory Bus
IRQs
PIC
CPU
idtr
IDT
INTR
cause N
handler
Mask points
255