1. What have mr aldred’s dirty clothes got to do with the cpu
RISC vs CISC
What have mr aldred’s dirty clothes got to do with the cpu

2. Mr Aldred’s
Dirty Laundry

3. Folding a t shirt

4. You work in a Tokyo Laundry and there is loads of dirty laundry that needs to be washed, dried, and folded
It takes the washer for 30 minutes,
Drying takes 40 minutes,
Folding the clothes takes 20 minutes
Then pick up the second load and wash, dry, and fold, and repeat for the third and fourth loads and firth loads.
Supposing we started at 18:00 and worked as efficiently as possible, what time would you finish?
What is the finish time?
Create a diagram that shows this

7. What does a processor do?

8. High Level language to Machine code
We program in High Level Languages e.g. C++.
The CPU deals with machine code.
We need a compiler to convert from our High LL to an Assembly language which in turn is ‘Assembled’ into Machine Code. (LMC)
The complexity of the code the CPU can handle is higher for a CISC processor than a RISC processor.
The more we break a program down into smaller steps the longer the code gets.
The Python interpreter is a program which is compiled to machine code (i.e. bit patterns). When that program runs it interprets (i.e. decodes and executes) your Python program.

9. RISC
Reduced instruction set computing
Simple instructions are faster to process
What do these complex instruction do?
Take this number and store it
If the number that is loaded into the accumulator is equal to zero then break the loop
Make this more complex
Open the door
Stand up

10. RISC Reduced Instruction Set Computer Simple hardware
Further away from high level languages
Longer code requiring more RAM
Compiler has to do more work
Every operation takes place in one clock cycle.
Show the main points to the students
Ask each / groups to act / draw each statement - could model with playdoh, other students guess

11. CISC Complex Instruction Set Computer. More complex hardware
Closer to High Level Language
Less work for the compiler to do
Smaller code requiring less RAM
Some instructions take multiple clock cycles to complete.
Show the main points to the students
Ask each / groups to act / draw each statement - could model with playdoh, other students guess

12. Consider how to add two numbers
Load the first number from RAM into a register
Load the second number from RAM into a register
Add them together
Store the answer in a register.
2 + 3 = ?

13. Why use risc processors then ?
The physical construction of RISC chips is simpler. They need less complicated circuitry as they perform fewer instruction types.
Therefore they can be made…
Smaller
To use less power
To generate less heat

14. Speed
If we look at a single Fetch-Execute cycle a CISC processor would appear to be much faster as it only has to fetch and decode a single instruction.
However, that instruction may take it several cycles to complete.
A RISC processor would take one cycle per instruction.

15. Pipelines To speed up processors we can use pipelines.
To do this we need to break the Fetch –Execute cycle into stages, e.g.
fetch instructions from memory
read registers and decode the instruction
execute the instruction or calculate an address
access an operand in data memory
write the result into a register
Instead of taking (4 x 5 = 20) cycles the CPU can process 4 lines of code in just 8 cycles.

16. Why pipelines don’t work as well with CISC processors.
Each line of RISC code takes 1 cycle to execute.
CISC code can take 1, 2 or more cycles to execute.
Therefore the compiler has a harder job of queuing up the jobs in the pipelines of CISC processors.
The ‘larger’ commands, particularly branched commands can cause the pipelines to ‘stall’ which slows the computer down.

17. Key questions
What is the comparison between the laundry and the RISC processing
What are the RISC instructions
Does the Laundry task represent CISC?
Where is the pipelining comparison?
What impact does it have on the washing?
How could the Laundry Task be written for a CISC?

18. Discuss the relative merits of CISC and RISC architectures when a chip manufacturer is planning a new processor