Quartus II Software Design Series : Foundation

Quartus II Software Design Series : Foundation

Objectives Create a new Quartus® II project
Choose supported design entry methods Compile a design in Quartus II Locate resulting compilation information Assign design constraints (timing & pin) Perform timing analysis & obtain results Generate files for 3rd-party EDA simulation Configure an FPGA

Class Agenda Projects Design Entry Compilation Settings & Assignments
Exercise 1 Design Entry Exercise 2 Compilation Exercise 3 Settings & Assignments Timing Analysis Exercise 4 Simulation Exercise 5

Introduction to Altera & Altera Devices

The Programmable Solutions Company®
Programmable Logic Devices Tools Quartus® II software SOPC Builder DSP Builder Nios® II IDE Intellectual Property (IP) Signal processing Communications Embedded processors Nios II embedded processor

Programmable Logic Families
Structured ASIC HardCopy® II & HardCopy Stratix devices High & medium density FPGAs Stratix® III, Stratix lI & Stratix devices Low-cost FPGAs Cyclone® II & Cyclone devices FPGAs w/ clock data recovery Stratix II GX & Stratix GX devices CPLDs MAX® II, MAX 7000 & MAX 3000 devices Configuration devices Serial (EPCS) & enhanced (EPC)

Software & Development Tools
Quartus II Subscription Edition Stratix III, Stratix II & Stratix devices Stratix II GX & Stratix GX devices Cyclone II & Cyclone devices HardCopy II & HardCopy Stratix devices MAX II, MAX 7000S/AE/B, MAX 3000A devices Select older families Quartus II Web Edition Free version Not all features & devices included See for feature comparison

Design Methodology

Typical PLD Design Flow
Design Specification Design entry/RTL coding - Behavioral or structural description of design RTL simulation - Functional simulation (ModelSim®, Quartus II) - Verify logic model & data flow (no timing delays) LE M512 M4K I/O Synthesis - Translate design into device specific primitives - Optimization to meet required area & performance constraints - Quartus II, Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA Place & route - Map primitives to specific locations inside Target technology with reference to area & performance constraints - Specify routing resources to be used

Typical PLD Design Flow
tclk Timing analysis - Verify performance specifications were met - Static timing analysis Gate level simulation - Timing simulation - Verify design will work in target technology PC board simulation & test - Simulate board design - Program & test device on board - Use SignalTap II for debugging

Quartus II Design Software Feature Overview

Quartus II Design Software
Fully-integrated development tool Multiple design entry methods Logic synthesis Place & route Simulation Timing & power analysis Device programming

More Features MegaWizard® & SOPC Builder design tools
TimeQuest Timing Analyzer Incremental Compilation feature PowerPlay Power Analyzer tool NativeLink® 3rd-party EDA tool integration Debugging capabilities From HDL to device in-system 32 & 64-bit Windows, Solaris, & Linux support Multi-processor support Node-locked & network licensing options

Quartus II Operating Environment
Project Navigator Status window Message window

Main Toolbar Execution controls New file buttons Dynamic menus
Chip Planner Compiler report To reset views: Tools  Customize  Toolbars  Reset All Restart Quartus II software

Quartus II Projects

Quartus II Projects Description
Collection of related design files & libraries Must have a designated top-level entity Target a single device Store settings in Quartus II Settings File (.QSF) Create new projects with New Project Wizard Can be created using Tcl scripts

New Project Wizard Tcl: project_new <project_name> File menu
Select working directory Name of project can be any name; recommend using top-level file name Top-level entity does not need to be the same name as top-level file name Create a new project based on an existing project & settings Tcl: project_new <project_name>

Add Files Add design files Add user library pathnames
Graphic (.BDF, .GDF) AHDL VHDL Verilog EDIF Notes: Files in project directory do not need to be added Add top level file if filename & entity name are not the same Absolute & relative paths are supported Add user library pathnames User libraries MegaCore®/AMPPSM libraries Pre-compiled VHDL packages Tcl: set_global_assignment –name VHDL_FILE* <filename.vhd> Tcl: set_global_assignment –name USER_LIBRARIES <library_path_name> * Replace with VERILOG_FILE, EDIF_FILE, AHDL_FILE or BDF_FILE

Device Selection Choose device family
Choose specific part number from list or let Quartus II choose smallest fastest device based on filter criteria Tcl: set_global_assignment –name FAMILY “device family name” Tcl: set_global_assignment –name DEVICE <part_number>

EDA Tool Settings Choose EDA tools & file formats
Add or change settings later See handbook for Tcl command format

Done! Review results & click on finish

Opening an Existing Project
Double-clicking the .QPF file will auto launch Quartus II OR File  Open Project OR Select from most recent projects list Tcl: project_open <project_name>

Quartus II Project Files
Quartus II Project File (.QPF) Quartus II Defaults File (.QDF) Quartus II Settings File (.QSF)

Project & Default Files
Quartus II Project File (QPF) Quartus II version Time stamp Active revision(s) Quartus II Defaults Files (QDF) Stores Quartus II project setting & assignment defaults Example names: assignment_defaults.qdf or <revision_name>_ assignment_defaults.qdf QUARTUS_VERSION = “6.1" DATE = “08:37:10 November 05, 2006" # Active Revisions PROJECT_REVISION = "filtref“ PROJECT_REVISION = "filtref_new" COMPILE_FILTER.QPF

Quartus II Settings File (QSF)
Stores all settings & assignments (constraints) Uses Tcl syntax Can be edited manually by user See “Quartus II Settings File Reference Manual” for more details on QSF assignments & syntax Reorganize QSF based on categories (Project menu) Add user comments (#) & white spaces NEW assignments added to end of file Source other TCL/QSF files to organize assignments Note: See Appendix for more notes on using QSF file.

Project Management Project archive & restore Project copy Revisions

Project Archive Creates 2 files Example Uses
Compressed Quartus II Archive File (.QAR) Includes design files, QPF file & QSF file(s) Option to include databases (optional) Creates local QDF file for archive Archive activity log (.QARLOG) Example Uses File storage (e.g. version control) Project handoff Design files referenced from user libraries are included in archive Tcl: project_archive <project_name>

Project Archive (cont.)
Project Menu Database inclusion View files to be included in archive and select files to add to or remove from archive

Project Restore Decompresses .QAR into specified directory
Project Menu Archive file name Directory to receive decompressed project files Tcl: project_restore <archive_file>

Project Copy Copies & save duplicate of project in new directory
Project file (.QPF) Design files Settings files Example Use Duplicating work before editing design files User libraries are not copied Project Menu

Revisions Explore new sets of constraints or compile options without losing prior Allows designer to try different options on same design files Compare results between revisions

Creating a Revision Project  Revisions
Base Revision on Any Previous Revision Create New Revision The Revisions dialog box allows you to MANAGE your revisions Talk About: Set Current Create Revision Name Based on revision Description Box Type Revision Description Tcl: create_revision <revision_name>

Project Revision Support
QSF created for each revision <revision_name>.QSF Active revision names stored in QPF Text file created for each revision <revision_name>_description.TXT Active Revisions will change to Revisions in Q4.1 Design Files are not controlled… not like Clearcase or RCS Easily switch between revisions Tcl: project_open –revision <revision_name> <project_name> Tcl: set_current_revision <revision_name>

Compare Revisions Detailed summary of revision assignments and results
To open, click on Compare button in Revision dialog box Export to CSV file Compare results with other projects

Please go to Exercise 1 in the Foundation Exercise Manual

Exercise Summary Created a new project using the New Project Wizard

Projects Entry Summary
Projects necessary for design processing Use New Project Wizard to create new projects Use Project Navigator to study file & entity relationships within project Project archive, copy and revisions provide easy-to-use project management

Project Support Resources
“Managing Quartus II Projects” chapter in Quartus II Handbook

Design Entry

Imported from 3rd-Party EDA tools
Design Entry Methods Quartus II Text Editor AHDL VHDL Verilog Schematic Editor Block diagram file Graphic design file Memory Editor HEX MIF 3rd-party EDA tools EDIF 2 0 0 Verilog Quartus Mapping (.VQM) Mixing & matching design files allowed Top-level design files can be schematic, HDL or 3rd-Party netlist file Block file Symbol Text Imported from 3rd-Party EDA tools Generated within Quartus II .v, vlg, .vhd, .VHDL, vqm .edf .edif .v .vhd .tdf .bsf .bdf .gdf Top-Level File

Altera Megafunctions Pre-made design blocks Benefits Two versions
Configurable settings add flexibility “Drop-in” support to accelerate design entry Pre-optimized for Altera architecture Two versions Quartus II megafunctions Intellectual Property (IP) megafunctions

Quartus II Megafunctions
Free & installed with Quartus II software Non-encrypted functions written in AHDL HDL simulation models installed in Quartus II libraries Two types Altera-specific megafunctions (begin with “ALT”) Library of paramerterized modules (LPMs) Standardized logic functions Examples Multiply-accumulate (ALTMULT_ACCUM) On-chip RAM/ROM (ALTSYNCRAM) PLL (ALTPLL) DDR/QDR memory interface (ALTMEMPHY) Counter (LPM_COUNTER)

IP Megafunctions Must purchase license to use in finished design
Logic for IP function is encrypted Two types MegaCore® IP Developed by Altera Install with Quartus II software or download/install individually from Altera Megafunctions Partner Program (AMPP℠) IP Developed by 3rd-Party IP vendors & certified by Altera Contact vendor for evaluating and licensing function All MegaCore functions & some AMPP functions support OpenCore® Plus feature Develop design using free version of core HDL simulation models provided with IP Generate time-limited configuration/programming files

Example MegaCore IP Triple-Speed Ethernet MAC FIR Compiler
Fast Fourier Transform DDR2 Memory Controller CRC Compiler PCI Compiler

MegaWizard Plug-in Manager
Eases implementation of megafunctions Tools  MegaWizard Plug-In Manager

MegaWizard Example Multiply-Add megafunction
Locate Documentation in Quartus II Help or the Web Multiply-Add megafunction Three step process to configure megafunction Resource Usage

MegaWizard Output File Selection
Default HDL wrapper file Selectable HDL instantiation template VHDL component declaration (CMP) Quartus II symbol (BSF) Verilog black box Behavioral waveform (.html)

Memory Editor Create or edit memory initialization files in Intel HEX (.HEX) or Altera-specific (.MIF) format Design entry Use to initialize your memory block (ex. RAM, ROM) during power-up Simulation Use to initialize memory blocks before simulation or after breakpoints

Create Memory Initialization File
File  New  Other Files tab 3) Memory space graphic opens 1) HEX format or MIF format 2) Select Memory Size

Change Options View options of memory editor
View  select from available options

Edit Contents Edit contents of memory file
Select address location & type in a value OR Select the address & right-click to select fill option from menu Copy & paste from spreadsheet Edit contents of memory file Save memory file as .HEX or .MIF file Specify custom cell fill Repeating sequence Increment/decrement count

Using Memory File In Design
Specify MIF or HEX file in MegaWizard May also specify MIF or HEX file in HDL using the ram_init_file attribute

Memory Size Wizard Need to edit size of memory file?
Use the memory size wizard (edit menu) Edit word size Edit number of words Specify how to handle word size change Increasing word size Pad words Combine words Decreasing word size Truncate words from left Truncate words from right

EDA Interfaces Introduction
Interface with industry-standard EDA tools that generate a netlist file EDIF (.EDF) Verilog Quartus Mapping (.VQM) To import netlist files Specify EDA tool in Quartus II Instantiate block(s) in design Add .EDF/.VQM file(s) to Quartus II project

3rd-Party Design Entry Tool Support
Mentor Graphics® LeonardoSpectrum™ Precision RTL Synthesis Synplicity Synplify Synplify Pro

Design Entry Summary Multiple design entry methods supported
Text (Verilog, VHDL, AHDL) 3rd-party netlist (VQM, EDIF) Schematic MegaWizard Plug-In Manager configures megafunctions & IP Memory Editor allows generation of memory initialization files 3rd-party EDA tools supported for design entry & synthesis

Design Entry Support Resources
Quartus II Handbook chapters “Design Recommendations for Altera Devices” “Recommended HDL Coding Styles” 3rd-Party EDA tool chapters (Volume 1, Section 3) Training courses & demonstrations VHDL & Verilog Basics (online courses) Introduction & Advanced HDL courses

Quartus II Compilation

Quartus II Full Compilation Flow*
Design Files Analysis & Elaboration Constraints & Settings Synthesis Functional Simulation Functional Netlist Constraints & Settings Fitter Assembler Programming & Configuration files (.sof/.pof) Different tools have different definitions for what it means to “compile”. In general terms it means to process the input. In Quartus II that means it will analyze the input files for errors, build your design entry database, synthesize logic, run the fitter and generate output in the form of programming files and timing information. QII will also generate output simulation netlist files, if set up to do so. During synthesis and fitting of the design, any constraints or settings that have been applied to the project or revision will be used to guide the design compilation. TimeQuest Timing Analysis EDA Netlist Writer Gate-Level Simulation Post-Fit Simulation Files (.vho/.vo) *This is the typical flow. Other module executables will be added if additional software features are enabled.

Processing Options Start Compilation Performs full compilation
Start Analysis & Elaboration Checks syntax & builds database only Performs initial synthesis Start Analysis & Synthesis Synthesizes & optimizes code Start Fitter Places & routes design Generates output netlists Start Assembler Start TimeQuest Timing Analyzer Start I/O Assignment Analysis Start Design Assistant

Status & Message Windows
Status bars scroll to indicate compiler modules executed and compilation progress Message window displays informational, warning & error messages

Message Suppression Hides messages from current & future compiles
Ex. Known synthesis warning message already investigated Displays suppressed messages on different tab in message window Stores suppression rules in <revision_name>.SRF file Choose Suppress Right-Click on Message Suppress Exact or Similar Messages

Message Suppression Manager Tool
Use to View all suppressible messages View/add/remove suppression rules View messages suppressed for current & future compiles

Viewing Compilation Results
Quartus II graphical tools available for Understanding design processing Verifying correct design results Debugging incorrect results Compilation Report Viewers RTL & Technology Map State Machine Chip Planner Resource Property Editor

Compilation Report Graphical window containing all compilation processing information Resource Usage Device pin-out Settings and constraints applied Messages Opens automatically when processing begins Recommendation: Go through report for a design to get sense of information being provided Information also available as text files in project directory Ex. <project_name>.fit.rpt & <project_name>.map.rpt Many times I get questions about where certain information can be found and most often the response is, “There’s a table for that in the compilation report.” So, we recommend taking a design you have compiled and just going through the report to see what information is being provided to you. If you don’t understand a table, you can either assume you don’t need it (hee hee) or you can simply send a question to mysupport. They will be happy to explain the purpose of one of the reports.

Compilation Report Window  Detach Window to release from Quartus II workspace Each compiler executable generates separate folder

Example: Source Files Read
Source Files Read table lists all design files (user-coded & library) used during last compilation along with files’ type and location

Example: Resource Usage
Several tables in Resource Section detail how much of FPGA resources available and used

RTL Viewer Graphically represents results of synthesis
Tools Menu  Netlist Viewers Schematic View Hierarchy List Note: Must Perform Elaboration First (e.g. Analysis & Elaboration OR Analysis & Synthesis)

Technology Map Viewers
Graphically represents results of mapping & fitting Tools Menu  Netlist Viewers Hierarchy List Schematic View Note: Must Run Synthesis and/or Fitting First

Uses RTL Viewer Technology Map Viewers
Visually checking initial HDL synthesis results Before any Quartus II optimizations Locating synthesized nodes for assigning constraints Debugging verification issues Technology Map Viewers Analyze critical timing paths graphically Delay values displayed if timing Locating nodes & node names after optimizations Assigning constraints Debugging

State Machine Viewer Tools menu  Netlist Viewers
Use drop-down to select state machine State Flow Diagram Highlighting state in state transition table highlights corresponding state in state flow diagram State Transition/Encoding Table

Compilation Summary Compilation includes synthesis & fitting
Compilation report contains detailed results Run RTL, Technology & State Machine Viewers to analyze Quartus II results Settings & assignments control compilation Pin assignments can be performed in many ways

Compilation Support Resources
Quartus II Handbook chapters “Quartus II Incremental Compilation for Hierarchical & Team-Based Design” “Area & Timing Optimization” “Timing Closure Floorplan” Training Courses and Demonstrations Pin Planner demonstration

Settings & Assignments

Synthesis & Fitting Control
Controlled using two methods Settings Project-wide switches Assignments (i.e. logic options; constraints) Individual entity/node controls Accessed using Assignments menu Stored in QSF file for project/revision

Settings Project-wide switches Examples
Device selection Synthesis optimization Fitter settings Physical synthesis Design Assistant Located in Settings dialog box (Assignments menu)

Settings Dialog Box Change settings Top-level entity Target device
Add/remove files Libraries VHDL ’87 or ‘93? Verilog ‘95, ’01 or SystemVerilog? EDA tool settings Timing settings Compiler settings Synthesis settings Fitter settings Simulator settings Tcl: set_global_assignment –name <assignment_name*> <value> *See handbook for individual assignment names

Compilation Process Smart compilation(1)
2 Smart compilation(1) Skips entire compiler modules when not required (i.e. elaboration, synthesis, etc.) Saves compiler time Uses more disk space Generate version-compatible database(2) Tcl: set_global_assignment –name SMART_RECOMPILE ON

Version-Compatible Database
Recommended if migrating design between versions of Quartus II software Exports a database from one version that can be imported directly into another version Use to preserve compilation results between Quartus II software versions Re-running timing analysis or simulation with updated timing models Two methods to create Settings dialog box Project menu Tcl: set_global_assignment –name AUTO_EXPORT_VER_COMPATIBLE ON Tcl: set_global_assignment –name VER_COMPATIBLE_DB_DIR <directory_name>

Synthesis Netlist Optimizations
Further optimize netlists during synthesis Types WYSIWYG primitive resynthesis Gate-level register retiming Created/modified nodes noted in Compilation Report

WYSIWYG Primitive Resynthesis
Unmaps 3rd-party atom netlist back to gates & then remaps to Altera primitives Unavailable when using integrated synthesis Considerations Node names may change 3rd-party synthesis attributes may be lost Preserve/keep Some registers may be synthesized away Tcl: set_global_assignment –name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON

Gate-Level Register Retiming
Moves registers across combinatorial logic to balance timing Trades between critical & non-critical paths Makes changes at gate level Tcl: set_global_assignment –name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON

Fitter Settings Compilation speed/fitter effort Standard fit
Highest effort Longest compile time Fast fit Faster compile but possibly lesser design performance Auto fit Compile stops after meeting timing Conserves CPU time Will mimic standard fit for hard-to-fit designs Default for new designs One fitting attempt Compilation Speed : Reduce compilation time, may also reduce performance Tcl: set_global_assignment –name FITTER_EFFORT “<Effort Level>”

Physical Synthesis Re-synthesis based on fitter output
Makes incremental changes that improve results for a given placement Compensates for routing delays from fitter

Physical Synthesis Effort Types
Combinational logic Asynchronous signal pipelining Register duplication Register retiming Effort Trades performance vs. compile time Normal, extra or fast New or modified nodes appear in Compilation Report Tcl: set_global_assignment –name PHYSICAL_SYNTHESIS_EFFORT <Effort Level>

Combinational Logic Swaps look-up table (LUT) ports within les to reduce critical path LEs a LUT LUT f g a e c d b b - critical c d LUT e f g Tcl: set_global_assignment –name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON

Asynchronous Signal Pipelining
Adds pipeline registers to asynchronous clear or load signals in very fast clock domains aclr D Q Added pipeline stage aclr aclr aclr D Q Global clock delay Tcl: set_global_assignment –name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON

Duplication High fan-out registers or combinatorial logic duplicated & placed to reduce delay N Tcl: set_global_assignment –name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON

Assignments (Logic Options)
Individual switches applied to I/O, internal nodes or hierarchy blocks Use Assignment Editor to manage assignments Example assignments Optimization Technique PCI I/O Output Pin Load Must perform at least analysis & elaboration to obtain hierarchy & node information

Assignment Editor (AE)
Provides spreadsheet assignment entry & display Can copy & paste from clipboard Assignments Menu Enable/disable individual assignments Sort on columns Assignment Editor toolbar Customizable columns

Cross-Probing to Assignment Editor
Virtually all windows & tools cross-probe (locate) to Asssignment Editor Examples Project Navigator Message window Compilation Report Design files To invoke Assignment Editor: Highlight object/message Right-click Select Locate  Locate in Assignment Editor* *Note: Assignment Editor pre-filled with target node/pin name

Using Assignment Editor
Double-click cells to edit or type name directly Launch node finder or select from assignment groups Select assignment from drop-down menu & set value

Editing Multiple Assignments
Use Edit bar Editing multiple I/O standards at once

Node Finder Start displays nodes meeting search criteria
Search by name using wildcards (? or *) Use filter to select the nodes to be displayed Locate nodes in a certain level of hierarchy List of nodes in selected entity & lower levels of hierarchy Select nodes in Nodes Found box (left side) & use arrows to move to Selected Nodes (right side)

Export CSV File Assignments (Excel)
Export to CSV file (File menu) Import data into Excel

Available Logic Options (Assignments)
Go to Quartus II Help (Index) Type in “Logic Options” Click on “list of” Supported devices shown for each assignment

Updating QSF File QSF not updated automatically when constraint entered or Assignment Editor is saved QSF updated when Project is saved (File menu) Beginning of compilation Change behavior to updating assignments immediately (Tools menu  Options  Processing) Will impact software performance due to file accesses

Design Assistance Quartus II tools available to help improve designs
Design Assistant Optimization Advisors Timing Resource Power

Design Assistant Checks for potential design issues
If enabled, executes automatically during compilation May also run separately from Processing menu Checks for potential design issues Clocks Reset Synchronous design structures Timing closure Asynchronous clock domain data transfers

Optimization Advisors
Provide design-specific recommendations (feedback) on optimizing designs Three types Timing optimization Resource optimization Power optimization

Example Optimization Advisor
Problem area identified Three stages of recommendations to try in order Description of recommended settings Green checkmark indicates settings already in use Links to adjust settings

Settings & Assignments Summary
Settings & Assignments allow a designer to control how a design is synthesized, placed & routed Use the Settings dialog box to adjust project-wide settings Use the Assignment Editor to enable/disable individual assignments targeting hierarchy blocks, internal nodes or I/O The Quartus II software provides features such as the Design Assistant & Optimization Advisors to help improve design results

Design Analysis Support Resources
Quartus II Handbook chapters “Area & Timing Optimization” “Power Optimization” “Assignment Editor” “Netlist Optimizations & Physical Synthesis” Training Courses and Demonstrations Optimization Advisor demonstration

Simulation

Quartus II Simulation Simulator Method & Features Overview
Simulator Settings VWF File Creation Simulation Output 3rd Party Simulation

Supported Simulation Methods
Quartus II VWF (Vector Waveform File) Primary Graphical Waveform File VEC (Vector File) Text-Based Input File SCF (Simulator Channel File) MAX+PLUS II Graphical Waveform File TBL (Table File) Text-Based Output File from Quartus II or MAX+PLUS II Tcl/TK Scripting 3rd Party Simulators Verilog/VHDL Testbench

Simulator Features Converts VWF into HDL Testbench
Generates HDL Testbench Template Supports Breakpoints Performs Automatically Adding Output Pins to Output Waveform File Checking Outputs at End of Simulation

Assignments  Settings  Simulator
Simulator Settings Assignments  Settings  Simulator Mode Input File Period Options

Simulator Mode Functional Timing Type: RTL Uses Pre-Synthesis Netlist
Type: Gate-Level or Post-Place & Route Uses Fully Compiled Netlist

Simulator Input & Period
Specifies Stimulus & Length of Simulation Period Run Simulation until End of Stimulus File Specify Stimulus File Enter End Time

Simulator Options Automatically Add Output Pins to Simulation
Compares Simulation Outputs to Outputs in Stimulus File Reports Setup & Hold Violations Monitors & Reports Simulation for Glitches Reports Toggle Ratio Generates Signal Activity File for PowerPlay Power Analyzer

Create New Vector Waveform File
Select File  New  Vector Waveform File (Other Files Tab)

Insert Nodes Select Insert Node or Bus (Edit Menu) VWF Must Be Open
Use Node Finder

Specify End Time Maximum Length of Simulation Time Edit Menu

Insert Time Bars Set One Time Bar as Master Insert Other Time Bars
Relative to Master Absolute Specify Time Bar Time Bar Set Master Time Bar

Draw Stimulus Waveform
Highlight Portion of Waveform to Change Overwrite Value with Desired Value Highlight Waveform Overwrite Value Toolbar Shortcuts

Overwrite Waveform Signal Values
1 = Forcing ‘1’ 0 = Forcing ‘0’ X = Forcing Unknown U = Uninitialized Z = High Impedance H = Weak ‘1’ L = Weak ‘0’ W = Weak Unknown DC = Don’t Care

Overwrite Waveform Patterns
Clock Enter Period & Duty Cycle Counting Pattern Enter Count Timing Enter Start Value & Increment Arbitrary (Group) Value Random Value

Waveform to Testbench Generator
Converts VWF into HDL Testbench

Testbench Template Generator
Generates HDL Testbench Template User Inserts Test Stimulus

Before Functional Simulation
Perform Generate Functional Simulation Netlist (Processing Menu) Creates Pre-Synthesis Netlist Fails Simulation if Not Performed

Starting Simulation Processing Menu  Start Simulation Scripting

Simulator Report Displays Simulation Result Waveform
View Simulation Waveform Result Waveform

Comparing Waveforms Select Compare to Waveforms (View Menu)
Simulation Waveform Must Be Open Select VWF Comparison File

Compared Waveforms (Simulator Report)
Original Waveforms (Ctrl+1) Compared File Waveforms (Ctrl+2) Both Sets of Waveforms (Ctrl+3)

Processing  Simulation Debug  Breakpoints
Interrupts Simulation at Specified Points Consists of 2 Parts Equation (Condition) Action Stop Give Error Give Warning Give Info Processing  Simulation Debug  Breakpoints Click on condition to Build Equation

Breakpoint Conditions
<Node> <Operator1> <Value> Single Condition Ex. ena = 1 Time = <Value> time = 500ns <Condition> <Operator2> <Condition> Complex Tests ena = 1 && time > 500ns

Breakpoint Equations (cont.)
Node Opens Node Finder Operator1 <, >, = Operator2 && (AND) || (OR)

Example Breakpoint Enable/Disable Breakpoints Name Breakpoint
Arrange Order of Breakpoints

Using 3rd Party Simulators
Mentor Graphics ModelSim Cadence VERILOG-XL NC-Verilog NC-VHDL Synopsys VCS VSS Scirocco

Specify Simulator Select EDA Tools Settings Assignments Menu
Select Simulation Tool Generate Power Input File

Generating 3rd-Party Netlists
Full Compilation Execute Process Individually Processing Menu  Start  Start EDA Netlist Writer Generates Files without Full Compilation Scripting

3rd Party Simulation Files
Functional Simulation Use 220models & altera_mf Megafunction Model Files VHDL Timing Simulation Use Quartus II-Generated VHO & SDO Files Use <device_name>_ATOMS.VHD & <device_name>_ATOMS_COMPONENTS.VHD Files Located in eda\sim_lib Directory Verilog Timing Simulation Use Quartus II-Generated VO & SDO Files Use <device_name>_ATOMS.VO File

Simulation Exercise Summary
Prepared for Simulation Created VWF File Performed Functional Simulation Viewed Simulation Results

Simulation Summary Functional & Timing Simulation
Creating a Vector Waveform File

Programming/Configuration

Programming/Configuration
Setting device options Assembler module Programmer & chain description file Programming directly with Quartus II File conversion Creating multi-device programming files

Setting Device Options
Assignments  Device  Device & Pin Options Device options control configuration & initialization of device

General Tab Device options not dependent on configuration scheme (off by default) Enable device-wide clear Enable device-wide output enable Enable initialization done output pin

Other Device & Pin Option Tabs
Configuration Generates correct configuration & programming files every compilation Enables special features of configuration devices Enable programming file compression Set configuration clock frequency Programming Files Output files always created POF (programming object file) SOF (SRAM object file) Other selectable output files Jam (jedec stapl) JBC (JAM byte-code) RBF (raw binary file) HEXOUT (intel hex format) Dual-purpose pins Selects usage of dual-purpose pins after configuration is complete Unused pins Indicates state of all unused I/O pins after configuration is complete Error detection CRC Enables internal CRC circuitry & frequency Capacitive Loading Sets default capacitive loading for each I/O standard Board Trace Model Sets default board trace model characteristcs for each I/O standard (Stratix II only)

Quartus II Assembler Module
Generates all configuration/programming files As selected in device & pin options dialog box Ways to run assembler Full compilation Execute assembler individually Processing menu  Start  Start Assembler Generates files without full compilation Switching configuration devices Enabling/disabling configuration device feature Scripting

Open Programmer Enables device programming
Byteblaster™ II or byteblastermv™ cables Usb-blaster Masterblaster™ cable APU (Altera programming unit) Opens chain description file (.CDF) Stores device programming chain information

When adding files, the device for that file is automatically chosen
CDF File Lists devices & files for programming or configuration Programs/configures in top-to-bottom order When adding files, the device for that file is automatically chosen

Example CDF Files Single device chain Multiple device chain

Programmer Toolbar Start programming Auto detect devices in JTAG chain
Add/remove/change devices in chain Add/remove/changes files in chain Change order of files in chain Setup programming hardware

Setting Up Programming Hardware
Click on the Hardware Setup Button Use Drop-Down to Select Programming Hardware

Chain Programming Modes
JTAG JTAG chain consisting of Altera & non-Altera devices Passive serial Altera FPGAs only Active serial Altera serial configuration devices In-socket programming CPLDs & configuration devices in APU

Programming Options Program/configure
Applies to all devices Verify, blank-check, examine & erase Configuration devices MAX II, MAX 7000 & MAX 3000 Security bit & ISP clamp To program, verify, blank-check, examine, or erase a device, check the appropriate boxes

Bypassing Devices In JTAG Chain (1)
Method 1 : Add programming file & leave Program/Configure box unchecked

Bypassing Devices In JTAG Chain (2)
Method 2 : Click on Add Device button & select device to leave the programming file field blank

Adding Non-Altera Device to Chain
Click New & create user-defined devices to add non-Altera devices to chain

Starting The Programmer
Click program button once CDF file & hardware setup are complete Progress field shows the percentage of completion for the programmer

Converting SOF Programming Files
Creates multi-device .POF for enhanced configuration devices Enables compression & other configuration device options

Programming/Configuration Summary
Setting device options Generating programming files Programming device or devices in chain Converting programming files

Programming Support Resources
Programming Center Configuration Center

Timing Analysis

Timing Analysis Agenda
Standard/Single Clock Analysis Timing Assignments Global & Individual Fast Timing Model Analysis Early Timing Estimation

Principles of Static Timing Analysis
Every path has a start point and an end point: Start Points: End Points: ONLY FOUR POSSIBLE TIMING PATHS Input ports Clock pins Output ports Data input pins of sequential devices IN * D Q clk D Q clk * * OUT CLK combinational delays*

Running Timing Analysis
Automatically Use Full Compilation Manually Processing Menu  Start  Start Timing Analysis Tcl Scripts Uses Changing Speed Grade Annotating Netlist with Delay Information

Reporting Timing Results
Timing Analyzer Section of Compilation Report Summary Timing Analyses Clock Setup (fmax) Clock Hold tsu (Input Setup Times) th (Input Hold Times) tco (Clock to Out Delays) tpd (Pin to Pin Combinatorial Delays)

Standard/Single-Clock Analysis
Performed Automatically during Each Compile Detects Clocks Automatically If No Assignments Are Made Single or Multiple Asynchronous Clock Domains Analyses Clock Setup & Hold Input Pin Setup/Hold Time Output Pin Clock-to-Output Time

Clock Setup (fmax) Worst-Case Clock Frequency
Without Violating Internal Setup Times B C tco tsu E Clock Period Note: Clock Period = Clock-to-Out + Data Delay + Setup Time - Clock Skew = tco + B + tsu - (E - C) fmax = 1/Clock Period

Clock Setup (fmax) Tables
Fmax Values Are Listed in Ascending Order; Worst Fmax Is Listed on the Top Worst fmax Source, Destination Registers & Associated Fmax Values Select Clock Setup

fmax Analysis To Analyze the Path More Closely
Highlight, Right-Click Mouse & Select List Paths Similar Steps for All Timing Path Analysis in Quartus II

fmax Analysis Details Messages Window (System Tab) in Quartus II tco
Data Delay (B) Destination Register Clock Delay (E) Source Register Clock Delay (C) Setup Time (tsu) Clock to Output (tco) tco B tsu C E 1 = MHz 0.384 ns ns ns ns Clock Period

Locate Delay Path in Floorplan
Right-Click & Select Locate Compilation Report Notes: May Also Locate to Floorplan from Message Window Use Similar Procedure for All Timing Path Analysis

Locate Delay Path in Floorplan
3.807 ns Is the Total Path Delay

Locate Delay in Technology Viewer
Total delay: ns

Clock Hold Analysis Checks Internal Register-Register Timing
Report Occurs Only When Hold Violations Occur Results When Data Delay (B) is Less than Clock Skew (E-C) Non-Global Clock Routing Gated Clocks tco +B C tco B th C Data E E E - C th Clock Period

Hold Time Violations Table
Discover Internal Hold Time Issues before Simulation Not Operational: Clock Skew > Data Delay List Paths Window

I/O Setup (tsu) & Hold (th) Analyses
Data delay intrinsic tsu & hold tsu th Clock delay tsu = data delay - clock delay + intrinsic tsu th = clock delay - data delay + intrinsic th

I/O Clock-to-Output Analysis (tco)
intrinsic tco Data delay tco Clock delay clock delay + intrinsic tco + data delay = tco

I/O Timing Analyzer tsu, tco, th Will All Show up in the Timing Analyzer Report Register Name Clock Name Select Parameter Value Pin Name Note: Timing Analysis of tpd is similar

Timing Analysis Options
Used to Expand/Limit which Paths Are Analyzed/Displayed Examples Recovery & Removal Enable Clock Latency Reports Detected Clock Offset as Latency Affecting Clock Skew Clock Setup/Hold Relationships Maintained Ex. Inserting Clock Delay Using PLLs Enables Latency Timing Assignments (Discussed Later) Timing Constraint Check Determines if Any Paths Not Constrained by Timing Assignment

Timing Analysis Options (cont.)
Examples (Cont.) Combined Fast/Slow Timing Analysis (Discussed Later) Global Cut Timing Options (On by Default) Cut Paths between Unrelated Clock Domains Cut Off Feedback from I/O Pins Cut Off Read during Write Signal Paths Timing Analyzer Options Display Paths that Do Not Meet Timing Only

Recovery & Removal CLOCK t_removal CLEAR Reset (Data) Arrival Time t_recovery Setup/Hold Analysis Where Data Path Feeds Register Asynchronous Control Port (Clr/Pre/Load) Primetime’s Definitions Recovery Minimum Length of Time after an Asynchronous Control Signal Is Disabled that an Active Clock Edge Can Occur Removal Minimum Length of Time Asynchronous Control Signals Must Stay Asserted after an Active Clock Edge

Cut Off Feedback from I/O Pin
Breaks Bidirectional I/O Pin from Analysis When On, Paths A & B Are Valid; C Is Not When Off, Paths A, B, & C Are Valid I/O Pin Register 1 Register 2 A B Q D C clk

Timing Options Assignments  Settings  Timing Requirements & Options

Timing Analyzer Options
Assignments  Settings  Timing Analyzer List 200 Paths List Paths with Fmax Less than 250 MHz List Paths with Tsu Greater than 3 ns

Timing Analysis Exercise Summary
Performed Single Clock Timing Analysis Viewed Details on Timing Paths Message Window Floorplan Technology Viewer

Class Summary Project creation Design entry techniques
Compilation & Design analysis Settings & Assignments Simulation Programming/configuration Timing analysis

Quartus II Software Design Series : Foundation

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Quartus II Software Design Series : Foundation

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