1. Basic Logic Design with Verilog HDL: Gate-Level Design on Combinational Circuits
Lecture note ver.1 by Chen-han Tsai
ver.2 by Chih-hao Chao
ver.3 by Xin-Yu Shi
ver.4 by Bo-Yuan Peng
ver.5 by Cheng-Zhou Zhan
ver.6 by Bo-Yuan Peng

2. Outline Introduction to Verilog HDL Syntax in Verilog HDL
Gate-Level Modeling
Test-Bench
Compilation and Simulation Tools

3. Outline Introduction to Verilog HDL Syntax in Verilog HDL
Gate-Level Modeling
Test-Bench
Compilation and Simulation Tools

4. What is Verilog HDL? Why using Hardware Description Language?
Design abstraction: HDL ←→ layout by human
Hardware modeling
Reduce cost and time to design hardware
Two Popular HDLs
VHDL
Verilog

5. What is Verilog HDL? Key features of Verilog
Supports various levels of abstraction
Behavior level
Register transfer level
Gate level
Switch level
Simulate design functions

6. Different Levels of Abstraction
Architectural / Algorithmic Level
Implement a design algorithm in high-level language constructs.
Register Transfer Level
Describes the flow of data between registers and how a design process these data.

7. Different Levels of Abstraction
Gate Level
Describe the logic gates and the interconnections between them.
Switch (Transistor) Level
Describe the transistors and the interconnections between them.

8. Simplified Hardware Design Flow
Verilog

9. Example: 1-bit Multiplexer

10. Gate Level Description
in1
in2
sel
out o1
iv_sel
a1_o
a2_o n1
Gate Level: you see only netlist (gates and wires) in the code.

11. Outline Introduction to Verilog HDL Syntax in Verilog HDL
Gate-Level Modeling
Test-Bench
Compilation and Simulation Tools

12. A Simple Verilog Code module name in/out port declaration syntax
port/wire
declaration
kernel hardware
gate-connection/
behavior

13. Module Basic building block in Verilog Module
Created by “declaration” (can’t be nested)
Used by “instantiation”
Interface is defined by ports
May contain instances of other modules
All modules run concurrently

14. Module Instantiation
instance example

15. Instances
A module provides a template from which you can create actual objects.
When a module is invoked, Verilog creates a unique object from the template.
Each object has its own name, variables, parameters and I/O interface.

16. Analogy: Module vs. Class
Format
module m_Name( IO list );
...
endmodule
class c_Name { };
Instantiation
m_Name ins_name ( port connection list );
c_Name obj_name;
Member
ins_name.member_signal
obj_name.member_data
Hierachy
instance.sub_instance.member_signal
object.sub_object.member_data

17. Port Connection Connect module port by order list
FA1 fa1(c_o, sum, a, b, c_i);
Connect module port by name (Recommended)
Usage: .PortName (NetName)
FA1 fa2(.A(a), .B(b), .CO(c_o), .CI(c_i), .S(sum));
Not fully connected
FA1 fa3(c_o, , a, b, c_i);

18. Verilog Language Rule Case sensitive Identifiers
Digits
Underscore _
Upper and lower case letters from the alplabet
Terminate statement/declaration with semicolon “;”
Comments
Single line: // it’s a single line comment example
Multi-line: /* When the comment exeeeds single line, multi-line comment is necesssary */

19. Data Type: Register Register Keyword: reg, integer, time, real
Event-driven modeling
Storage element (modeling sequential circuit)
Assignment in “always” block (LHS of expressions)

20. Data Type: Net
Net
Keyword: wire, wand, wor, tri, triand, trior, supply0, supply1
Doesn’t store value, just a connection
Input, output and inout ports are default “wire”

21. Four-valued Logic Value
Nets and registers in Verilog codes hold four-valued data
0 represent a logic ‘0’ or false condition
1 represent a logic ‘1’ or true condition z
Output of an undriven tri-state driver – High-Z value
Models case where nothing is setting a wire’s value

22. Four-valued Logic Value
Nets and registers in Verilog codes hold four-valued data x
Models when the simulator can’t (doesn’t) decide the value – un-initialized or unknown logic value
Initial state of registers
A wire is being driven to 0 and 1 simultaneously
Output of a gate with z inputs

23. Logic System Four values: 0, 1, x/X, z/Z (not case sensitive)
The logic value x denotes an unknown (ambiguous) value
The logic value z denotes a high-impedance value (High-Z value)
Primitives have built-in Logic
Simulators describe 4-value logic

24. Logic System: Example
0 1 X Z
1 0 1 X X
X 0 X X X
Z 0 X X X

25. Number Representation
Format: <size>’<base_format><number>
<size> - decimal specification of bits count
Default: unsized and machine-dependent but at least 32 bits
<base_format> - ' followed by arithmetic base of number
d or D – decimal (default if no base format given)
h or H – hexadecimal
o or O – octal
b or B – binary

26. Number Representation
Format: <size>’<base_format><number>
<number> - value given in base of base format
_ can be used for reading clarity
x and z are automatically extended

27. Number Representation
Examples:
6’b010_111 gives
8’b gives
4’bx01 gives xx01
16’H3AB gives
24 gives 0…
5’O36 gives 11110
16’Hx gives xxxxxxxxxxxxxxxx
8’hz gives zzzzzzzz

28. Number Representation
659 // unsized decimal
‘h 837ff // unsized hexadecimal
‘o7460 // unsized octal
4af // illegal syntax
4’b1001 // 4-bit binary
5’D 3 // 5-bit decimal
3’b01x // 3-bit number with unknown LSB
12’hx // 12-bit unknown
8’d -6 // illegal syntax
-8’d 6 // phrase as - (8’d6)
// underline usage
27_195_000
16’b0001_0101_0001_1111
32’h12ab_f001
// X and Z is sign-extended
reg [11:0] a;
initial
begin
a = ‘hx; // yields xxx
a = ‘h3x; // yields 03x
a = ‘h0x; // yields 00x
end

29. Net Concatenation Module B Module A Module C 3‘o7
Representations Meanings
{b[3:0],c[2:0]} {b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]}
{a,b[3:0],w,3’b101} {a,b[3] ,b[2] ,b[1] ,b[0],w,1’b1,1’b0,1’b1}
{4{w}} {w,w,w,w}
{b,{3{a,b}}} {b,a,b,a,b,a,b}

30. Operators Arithmetic Operators Relational Operators Equality Operators
Logical Operators
Bit-wise Operators
Unary Reduction
Shift Operators
Conditional Operators
Concatenations
+, -, *, /, %
<, <=, >, >=
==, !=, ===, !==
!, &&, ||
~, &, |, ^, ~^
&, ~&, |, ~|, ^, ~^
>>, << ?: {}
Excerpts from CIC training course: Verilog_9807.pdf

31. Operator Examples All bits are 0 logic false
Excerpts from CIC training course: Verilog_9807.pdf

32. Compiler Directives 'define 'include 'timescale 'define RAM_SIZE 16
Defining a name and gives a constant value to it.
'include
'include adder.v
Including the entire contents of other verilog source file.
'timescale
'timescale 100ns/1ns
Setting the reference time unit and time precision of your simulation.

33. System Tasks $finish $monitor $display
$monitor ($time,"%d %d %d",address,sinout,cosout);
Displays the values of the argument list whenever any
of the arguments change except $time.
$display
$display ("%d %d %d",address,sinout,cosout);
Prints out the current values of the signals in the
argument list
$finish
Terminate the simulation

34. Outline Introduction to Verilog HDL Syntax in Verilog HDL
Gate-Level Modeling
Test-Bench
Compilation and Simulation Tools

35. Gate Level Modeling Steps HDL: Hardware Description Language
Develop the Boolean function of output
Draw the circuit with logic gates/primitives
Connect gates/primitives with net (usually wire)
HDL: Hardware Description Language
Figure out architecture first, then write code. 35 35

36. Primitives Primitives are modules ready to be instanced
Smallest modeling block for simulator
Verilog build-in primitive gate
and, or, xor, nand, nor, xnor
prim_name #delay inst_name( out0, in0, in1,.... );
not, buf
prim_name #delay inst_name( out0, out1, ..., in0);
User defined primitive (UDP)
building block defined by designer 36 36

37. Case Study: Full Adder 37 37

38. Case Study: Full Adder
Co = AB + BCi + CiA 38 38

39. Case Study: Full Adder
sum = a  b  ci 39 39

40. Case Study: Full Adder Full Adder Connection Instance ins_c from FA_co
Instance ins_s from FA_sum 40 40

41. Outline Introduction to Verilog HDL Syntax in Verilog HDL
Gate-Level Modeling
Test-Bench
Compilation and Simulation Tools

42. Test Methodology Systematically verify the functionality of a model.
Procedure of simulation
Detect syntax violations in source code
Simulate behavior
Monitor results 42 42

43. Test Methodology 43 43

44. Verilog Simulator 44 44

45. Testbench for Full Adder
module t_full_add();
reg a, b, cin; // for stimulus waveforms
wire sum, c_out;
full_add M1 (sum, c_out, a, b, cin); //DUT
initial #200 $finish; // Stopwatch
initial begin // Stimulus patterns
#10 a = 0; b = 0; cin = 0; // Execute in sequence
#10 a = 0; b = 1; cin = 0;
#10 a = 1; b = 0; cin = 0;
#10 a = 1; b = 1; cin = 0;
#10 a = 0; b = 0; cin = 1;
#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 1;
#10 a = 1; b = 1; cin = 1;
end
endmodule 45 45

46. Summary Design module / DUT Test-bench Divide-and-Conquer
Partition the whole design into several parts
Architecture figure of each sub-module
Make architecture figures before you write Verilog codes
Create hardware design in gate-level or RT-level
Connection of sub-modules
Test-bench
Feed input data and compare output values at right timing slots
Usually describe in behavioral level
Not real hardware, just like software programming (e.g. C/C++) 46 46

47. Note Verilog is a platform How to write verilog well? Hardware
Support hardware design (design module)
Also support C/C++ like coding (test bench)
How to write verilog well?
Know basic concepts and syntax
Get a good reference codes (a person or some code files)
Form a good coding style
Hardware
Combinational circuits (today’s topic)
Sequential circuits (we won’t model them in this course) 47 47

48. Outline Introduction to Verilog HDL Syntax in Verilog HDL
Gate-Level Modeling
Test-Bench
Compilation and Simulation Tools

49. Workstations Why workstations? How to run tasks on the workstations?
Multiple Users, multiple tasking
Stable Operations
How to run tasks on the workstations?
Operating System: Unix-like
Example: Linux
Example: Solaris
User Interface
Text Mode
X-Window

50. Workstations Where are the workstations? http://cad.ee.ntu.edu.tw/
Please fill the application, and your account will be ready before 11/13.
NOTE: This account expires after this semester.
If you want to continue enjoying the resources on the workstations, contact the TA managing the IC design Lab to get more information.
Usually you need to attend the Special Projects held by the professors in ICS or EDA group

53. Workstations How can I connect to the workstations? PCMan? KKMan? No!
putty or pietty (Inherited from putty, dedicated to CJK environments)
putty download site:
pietty download site:
In the following examples, we will use putty.

58. IP or Domain Name
Session Name (the same as IP or Domain Name)
Username and Password
Port: 22

60. Workstations
To make the programs available, we need to execute the following command:
source /usr/spring_soft/CIC/verdi.cshrc
This command needs to be executed whenever you login.

62. Workstations Basic instructions Change Password: passwd
Log out: logout
Show processes: ps (processes and PIDs)
Delete a process: kill -9 PID

63. Workstations Useful commands man : manual page
ls : list a folder’s contents
ls –a : list all files (including the hidden files)
ls –aux : list all files with detailed information
cp : copy files from one folder/directory to another
cp filename1 filename2
cp –r : copy the whole folder to another
mkdir : create a folder
pwd : display your current path

64. Workstations More useful commands cd : Change folder
ps : display process status by process identification number and name
kill -9 PID: terminate a running process
kill
rm : delete files
rm –r : remove the whole folder
quota –v : show disk space
tar : pack and compress files
-cvf : for creating compressed file
-xvf : for extracting compressed file
mv : move or rename file
exit : turn the terminal off
logout

65. X-window Why X-window? How to use X-window?
Most important graphic user interface on UNIX and similar system
How to use X-window?
You need an X-window server to use the X-window.
Not an X-window client. An X-window client is a program with GUI that runs on the workstations.

66. X-window

67. X-window What X-window server can be used? X-Win32 XFree86 Xming
Student Order : US$69.95
XFree86
Free
Need Cygwin on MS Windows
Xming
Free for version , but donation necessary for version
Easy to setup
We will use this as an example

69. Download and install these two

72. X-window
Since X-window server runs on users’ clients, we usually need our clients to have public IP.
What if we are using private IP, say, wireless network for example?

73. 1. Type the DN then save
2. Select X11 preference setup

74. 3. Check “Enable X11 forwarding

75. An example Run firefox (“&” means “simultaneously”)
NOTE: DON’T DO IT OFTEN!
PID

77. Useful Editors vi gedit Powerful but not so user friendly
Suitable for advanced users
gedit
graphic user interface
Analogy with notepad in Windows
Suitable for beginners
We use this as the example

78. gedit

79. Verilog-XL and NC-verilog
Designed by Phil Moorby, the father of verilog
Interpreter of verilog
Designed for syntax checking and simulation
NC-verilog
Designed by Cadence
Inherited from Verilog-XL
In the following examples, we use NC-verilog.

80. Example: Full Adder and its test-bench
FA_co.v
module FA_co ( co, a, b, ci );
input a, b, ci;
output co;
wire ab, bc, ca;
and g0( ab, a, b );
and g1( bc, b, ci );
and g2( ca, ci, a );
or g3( co, ab, bc, ca );
endmodule
FA_sum.v
module FA_sum ( sum, a, b, ci );
input a, b, ci;
output sum;
xor g0( sum, a, b, ci );
endmodule

81. Example: Full Adder and its test-bench
FA_gatelevel.v
module FA_gatelevel ( sum, co, a, b, ci );
input a, b, ci;
output sum, co;
FA_co ins_c( co, a, b, ci );
FA_sum ins_s( sum, a, b, ci );
endmodule

82. Example: Full Adder and its test-bench
FA_tb.v
module FA_tb();
reg a, b, cin;
wire sum, c_out;
FA_gatelevel fa1 ( sum, c_out, a, b, cin );
initial #200 $finish;
initial begin
#10 a = 0; b = 0; cin = 0;
#10 a = 0; b = 1; cin = 0;
#10 a = 1; b = 0; cin = 0;
#10 a = 1; b = 1; cin = 0;
#10 a = 0; b = 0; cin = 1;
#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 1;
#10 a = 1; b = 1; cin = 1;
end
endmodule

83. Example: Full Adder and test-bench

84. Example: Full Adder and its test-bench
How to observe the designed circuit?
debussy

88. Select the files then Add

93. Example: Full Adder and its test-bench
How to observe the timing diagram?
$fsdbDumpfile("filename");
$fsdbDumpvars;
nWave (part of debussy)

99. Double-click all of the signals you want to observe