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EE 435 Spring 2017 http://class.ece.iastate.edu/djchen/ee435/2017
Lecture 1 Course Outline
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Instructors Lecture Instructor: Laboratory Instructor: Degang Chen
Office: 2134 Coover Hall VoicePhone: Laboratory Instructor: Nanqi Liu, Shravan Chaganti Office: 3011 Coover Hall Voice Phone:
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* * students # * *
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Degang Chen Jerry Junkins Chair of Electrical & Computer Eng
Degang Chen Jerry Junkins Chair of Electrical & Computer Eng. Director of Analog and Mixed-signal Design Center Iowa State University, Ames, IA BS in instrumentation and automation, 1984, Tsinghua University PhD in ECE, 1992, Univ. California, Santa Barbara John Pierce Instructor, Cal Tech, S’1992 At ISU since Fall 1992
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Recent Research Focuses
AMS Circuit Design Techniques Op amp performance enhancement techniques Matching improvement studies Data converters, temp sensors, biosensors, LDOs Analog Verification Verification against undesired operating points Verification against undesired oscillation mode 0 dppm analog fault coverage Test Algorithms for Time/Cost Reduction Linearity testing Spectral performance testing Jitter separation and characterization BIST, BIST-based Calibration, and BIST for Design
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Current graduate students/Interns
Yingying Chen: PhD, interned at Broadcom, joined Broadcom Yan Duan: PhD, interned at Altera, joined Intel Huanhuan Zhang: PhD, interned at Skyworks, joined Intel Bin Huang: PhD, interned at Maxim, joined Maxim Xu Zhang: PhD, interned at Skyworks, joining Qualcomm Chongli Cai: PhD, interned at Texas Instr., joining Apple You Li: PhD, interned at Texas Instruments Yuming Zhuang: PhD, interned at Skyworks, Analog Devices Zhiqiang Liu: PhD, interned at Broadcom Tao Chen: PhD, interned at Freescale Leandro Fuentes: PhD, interned at Allegro MicroSystems Hao Meng: PhD, Interned at GlobalFoundries Shravan Chaganti: PhD, Interned at Skyworks Abdullah Kafi: MS Nanqi Liu: PhD
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Companies that hired my students
Texas Instruments Broadcom Maxim Freescale Allegro TSMC Skyworks Qualcomm Analog Devices Linear Technology Maxlinear …
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Office hours Regular office hours: MWF11-12
I’ll post my weekly schedule on my door, you can pick any open slot and sign up for an office visit If there are 3 or more students make a request, we can have a group “help” session Time: TBA
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Analog Integrated Circuit Design
Course Information: Required Text: Analog Integrated Circuit Design by T. Carusone, D. Johns and K. Martin, Wiley, 2011 Errata: Focus materials: Amplifier design: Chapters 3, 4, 5, 6 Data converter: Chapters 15, 16, 17 Other materials: Noise, references, comparators Chapters 7, 9, 10
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Course Information: Reference Texts:
CMOS Analog Circuit Design, 3rd Edition by Allen and Holberg, Oxford, 2012 Analysis and Design of Analog Integrated Circuits-5th Edition Gray,Hurst,Lewis and Meyer, Wiley, 2009
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Course Information: Reference Materials:
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Catalog Description E E 435. Analog VLSI Circuit Design. (Same as Cpr E 435.) (3-3) Cr. 4. S. Prereq: 324, 330, 332, and either EE 322 or Stat 330. Basic analog integrated circuit and system design including design space exploration, performance enhancement strategies, operational amplifiers, references, integrated filters, and data converters. Non-major graduate credit.
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Course Coverage by Topics
Current mirrors and basic amplifiers Operational amplifier design and compensation Comparator design Voltage references Noise analysis Switches Nyquist rate D/A and A/D converters
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Relation to Grad Level Courses
EE501: CMOS analog IC design (operational amplifier design) EE504: power management EE505: Data Converter Design EE506: phase locked loops EE507: VLSI Communication Circuits EE508: Integrated Filter Design EE509: analog and mixed-signal testing and built-in self-test EE514: RF and Microwave Circuits, low noise amplifiers
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EE 514 EE 506 EE 507 EE 508 EE 509 EE 504 EE 505 EE 501 EE 435 EE 465 EE 330
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Grading Homework: 15% Midterm Exam: 15~20% Final Exam: 30~35%
Lab and Lab Reports: 10% Project 1 Report: 10% Project 2 Report: 15% Discretionary bonus: 5% Fixed Grading Scale: (max possible: 105%) A: > 90% A–: 85 – 89.9% B+: 80 – 84.9% B: – 79.9% B–: – 74.9% C+: 65 – 69.9% C: – 64.9% C–: – 55.9% F: < 50% 50%
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Grading Qualifications
You can have study groups for HW But write your own HW solutions and submit individually No late HW. Your lowest 2 HW scores will be dropped. No make-up exams, except for unforeseeable emergency that is well documented. Your own higher exam score will receive the higher %, and lower score the lower %
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Laboratory There will be weekly laboratory experiments.
The laboratory will be either on electronic measurements or on VLSI CAD design and simulation. A written report after each topic is completed Lab reports are for individual work
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Design Projects Everyone will design a two-stage op amp
Teams will design various digital to analog converters or analog to digital converters Additional details will be given after relevant material is covered in class. The option will exist to have these projects fabricated through the MOSIS program.
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Additional Comments E-mail communication is strongly encouraged
Personal visit to my office is also encouraged Either academic or non-academic Anytime is OK Classroom participation is strongly encouraged I prefer an interactive class I feel nervous when the class is too quiet So, do me a favor and ask questions and answer questions
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First week lab Electronic measurements Extra Cadence simulation lab
Required for everybody Finish in one week Report due at beginning of lab in second week Extra Cadence simulation lab Not required for people with B or better in EE330 Show simulation results to any instructor
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Student behavior expectations
Full attendance expected, except with prior-notified excuses On-time arrival Active participation Ask questions Answer questions from instructor or students Be cordial and considerate to students and TA Help each other in reviewing notes, HW, Matlab Promptly report/share problems/issues, including typos on slides, or misspoken words from instructor
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Prohibited behaviors Any foul languages or gestures
Comments to other students that are discriminatory in any form Any harassments as defined by the university Academic dishonesty No alcohol, drugs, or any other illegal / improper substances Snacks/drinks OK as long as you don’t spill and do clean up
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Accommodation/Assistance
Please let me know if you Have any special needs Have disability in any form Have any medical/mental/emergency conditions Have field trip / interview Have special requests Want me to adjust lecture contents/pace Can also consult me if you Would like to seek advice on any professional or personal issues Would like to have certain confidential discussions
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Collaboration And Helping Each Other
For tasks intended for group work, you are expected to find a partner and share the tasks among the group members. In a group project, effective teamwork is critical to maximize the productivity of the whole group. In the submitted work, identify components and indicate percentage contribution by each member to each component. For tasks not intended for group work, individual submission is required. In this case, you are encouraged to discuss among your friends on how to attack problems. However, you should write your own solution. Copying other people’s work is strictly prohibited.
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Academic dishonesty Cheating is a very serious offense. It will be dealt with in the most severe manner allowable under University regulations. If caught cheating, you can expect a failing grade and initiation of a cheating case in the University system. Basically, it’s an insult to the instructor, the department and major program, and most importantly, to the person doing the cheating. Just don't. If in doubt about what might constitute cheating, send to your instructor describing the situation. If you notice anyone cheating, please report it to the instructor or the TA. Do not deal with it yourself.
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Discrimination State and Federal laws as well as Iowa State University policies prohibit any form of discrimination on the basis of race, color, age, religion, national origin, sexual orientation, gender identity, sex, marital status, disability, or status as a U.S. veteran. Language or gestures of discriminatory nature will not be tolerated. Severe cases will be reported to appropriate offices. See ISU policies at Let us make every effort to work together and create a positive, collegial, caring, and all-supportive learning environment in our classroom, laboratory, TA office, and instructor office.
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Disability accommodation
Iowa State University is committed to assuring that all educational activities are free from discrimination and harassment based on disability status. All students requesting accommodations are required to meet with staff in Student Disability Resources (SDR) to establish eligibility. A Student Academic Accommodation Request (SAAR) form will be provided to eligible students. The provision of reasonable accommodations in this course will be arranged after timely delivery of the SAAR form to the instructor. Students are encouraged to deliver completed SAAR forms as early in the semester as possible. SDR, a unit in the Dean of Students Office, is located in room 1076, Student Services Building or online at Contact SDR by at or by phone at for additional information.
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Accommodation for religion based conflicts
Iowa State University welcomes diversity of religious beliefs and practices, recognizing the contributions differing experiences and viewpoints can bring to the community. Students with religion based conflict should talk to the instructor and appropriate university offices to request accommodations at the earliest possible time.
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