1. ARM Cortex-M4 MCU and STM32F4 Discovery board description
Embedded Systems Software Training Center
ARM Cortex-M4 MCU and STM32F4 Discovery board description
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2. Instructor Introduction
Matveev Alexey Igorevich
Senior software developer,
DSR corp.
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3. Objectives
Learn basics about ARM Cortex-M4 background and architecture
STM32F4 DISCOVERY board functional review
Development tools for ARM Cortex-M4
Getting started with STM32F407 configuration and programming.
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4. Agenda History and background of ARM CPUs
STM32F4 DISCOVERY board review
STM32F407VGT6 MCU functional review
Development tools for ARM programming
STM32F407 programming basics
Memory organization
Chipset frequency configuration
General Purpose Input/Output
Hardware Timers
Interrupt and exception handling
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5. History and background of ARM CPUs
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6. ARM company
ARM (Advanced RISC Machine, Acorn RISC Machine) - based on a reduced instruction set computing (RISC) architecture (RISC) developed by British company ARM Holdings.
Official site
The company doesn't produce CPUs and MCUs in silicone.
The company only designs CPU cores in Verilog (or VHDL) languages
Anyone who wants to build its own ARM SoC should buy core license. After that he is able to construct his own SoC (ASIC, FPGA + peripherals)
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7. ARM CPU evolution
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8. ARM CPU evolution (part1)
The main (well known in the embedded world) ARM old CPUs are:
ARM7 - for embedded applications (MCU)
30 – 75 MHz, up to 512 kB Flash, up to 128 kB RAM
No cache, no MMU, 3-stage pipeline.
ARM9E - for mobile applications
~ MHz, cache, MMU, DSP, external Flash and RAM
ARM11– for high-performance applications
~ 700 MHz, MMU, cache, 8-stage pipeline, DSP, FPU, ext. Flash and RAM
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9. ARM CPU evolution (part 2)
After re-branding ARM named their CPUs as Cortex-<character> .
ARM Cortex-M MCUs (Next generation of ARM7 and ARM9)
For embedded applications
ARM Cortex-R MCUs
For hard real-time applications
ARM Cortex-A CPUs (Next generation of ARM11)
For high-performance applications
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10. ARM CPU evolution (part 2)
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11. STM32F4 DISCOVERY KIT COPYRIGHT © 2016 DSR CORPORATION11

12. STM32F4DISCOVERY Reset button USB OTG ST-LINK/V2 Programming
tool
USB
OTG
Audio Jack
User button
STM32F407VGT6
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13. STM32F4DISCOVERY Hardware block diagram Top layout
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14. STM32F4DISCOVERY features
STM32F407VGT6 MCU featuring 1 MB of Flash memory, 192 KB of RAM
On-board ST-LINK/V2 with selection mode switch
Board power supply: through USB bus or from an external 5V
External application power supply: 3V and 5V
LIS302DL, ST MEMS motion sensor, 3-axis digital output accelerometer
MP45DT02, ST MEMS audio sensor, omnidirectional digital microphone
CS43L22, audio DAC with integrated class D speaker driver
Eight LEDs:
– LD1 (red/green) for USB communication
– LD2 (red) for 3.3V power on
– Four user LEDs, LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue)
– 2 USB OTG LEDs LD7 (green) VBus and LD8 (red) over-current
Two pushbuttons (user and reset)
USB OTG with micro-AB connector
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15. Useful links:
STM32F4DISCOVERY Product page:
User manual:
STM32F4DISCOVERY board firmware package, including 22 examples :
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16. STM32F407VGT6 MCU COPYRIGHT © 2016 DSR CORPORATION

17. ARM Cortex M4 core
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18. STM32F407VGT6 blocks
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19. STM32F407VGT6 core main features:
ARM 32-bit Cortex™-M4 CPU (168 MHz, 1 Mbyte of Flash memory, Kbytes of SRAM including 64-Kbyte of CCM data RAM);
3×12-bit A/D converters;
2×12-bit D/A converters;
General-purpose DMA: 16-stream DMA controller ;
Twelve 16-bit and two 32-bit timers with PWM or pulse counters;
Serial wire debug (SWD) & JTAG interfaces;
Up to 140 I/O ports with interrupt capability;
Up to 3 × I2C interfaces (SMBus/PMBus);
Up to 4 USARTs/2 UARTs;
Up to 3 SPIs (42 Mbits/s);
2 × CAN interfaces (2.0B Active);
USB 2.0 full-speed device/host/OTG controller;
10/100 Ethernet MAC with dedicated DMA;
8- to 14-bit parallel camera interface up to 54 Mbytes/s;
LCD parallel interface, 8080/6800 modes.
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20. Useful links:
STM32F407VG product page:
Reference manual including functional and register description:
Other documentation :
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21. Development tools and libraries
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22. Popular development tools for Cortex-M4
Atmel Studio by Atmel (based on Visual Studio and GNU GCC Toolchain)
Code Composer Studio by Texas Instruments
CoIDE by CooCox
Eclipse as IDE, with GNU Tools as compiler/linker, e.g. aided with GNU ARM Eclipse Plug-ins
GNU Tools (aka GCC) for ARM Embedded Processors by ARM Ltd - free GCC for bare metal
IAR Embedded Workbench for ARM by IAR
Keil MDK-ARM by Keil
Visual Studio by Microsoft as IDE, with GNU Tools as compiler/linker - e.g. supported by VisualGDB
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23. STM32F4 libraries
CMSIS – Cortex Microcontroller Interface Standard  vendor-independent hardware abstraction layer for the Cortex-M processor series and specifies debugger interfaces.
SPL – Standard Peripheral Library for STM32 Microcontrollers. Implements Hardware Abstraction Layer for STM32 peripherals. Often can be downloaded with CMSIS.
STM32Cube - Embedded software for STM32 F4 series (HAL low level drivers, USB, TCP/IP, File system, RTOS, Graphic - coming with examples running on ST boards). Modern version of STM32 library from STMicroelectronics.
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24. CMSIS - Cortex Microcontroller Software Interface Standard
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25. CMSIS description
CMSIS-CORE: API for the Cortex-M processor core and peripherals. It provides at standardized interface for Cortex-M0, Cortex-M3, Cortex-M4, SC000, and SC300.
CMSIS-DSP: DSP Library Collection
CMSIS-RTOS API: Common API for Real-Time operating systems.
CMSIS-SVD: System View Description for Peripherals. Describes the peripherals of a device in an XML file and can be used to create peripheral awareness in debuggers or header files with peripheral register and interrupt definitions.
CMSIS-DAP: Debug Access Port. Standardized firmware for a Debug Unit that connects to the CoreSight Debug Access Port. CMSIS-DAP is distributed as separate package and well suited for integration on evaluation boards. This component is provided as separate download. 
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26. Programming STM32F407 COPYRIGHT © 2016 DSR CORPORATION26

27. Memory organization:
At startup, boot pins are used to select one out of three boot options:
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
Memory access overview:
32-bit data bus;
4 Gb common memory space for flash, internal ram, peripherals, external ram, debug blocks, etc.;
Unaligned data access;
Bit-band method.
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28. The Cortex-M3/M4 registers
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29. Chipset frequency configuration
Three different clock sources can be used to drive the system clock (SYSCLK):
HSI oscillator clock signal is generated from an internal 16 MHz RC oscillator and can be used directly as a system clock, or used as PLL input.
HSE oscillator clock signal can be generated from external crystal/ceramic resonator or external user clock
Main PLL (PLL) clock featuring high speed system clock (up to 168 MHz) and clock for the USB OTG FS (48 MHz), the random analog generator (≤48 MHz) and the SDIO (≤ 48 MHz).
SYSCLK configuration for STM32F4DISCOVERY board:
SYSCLK (system_ stm32f4xx.h) = PLL_VCO / PLL_P
PLL_VCO(system_ stm32f4xx.h) = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
HSE_VALUE (stm32f4xx.h) = Hz
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30. GPIO configuration
Configuration registers: GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR;
Data registers: GPIOx_IDR and GPIOx_ODR;
Set/reset register: GPIOx_BSRR;
Locking register: GPIOx_LCKR;
Alternate function selection registers: GPIOx_AFRH and GPIOx_AFRL.
To configuring GPIO using SPL driver:
Include stm32f4xx_gpio.h in your project;
Enable the GPIO AHB clock using the following function RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
Configure the GPIO pin(s) using GPIO_Init();
To get the level of a pin configured in input mode use GPIO_ReadInputDataBit();
To set/reset the level of a pin configured in output mode use GPIO_SetBits()/GPIO_ResetBits();
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31. STM32F407 timers: General-purpose timers (TIM2 to TIM5)
-16-bit (TIM3 and TIM4);
-32-bit (TIM2 and TIM5);
- up, down, up/down auto-reload counters.
General-purpose timers (TIM9 to TIM14)
-16-bit auto-reload upcounter.
Advanced-control timers (TIM1&TIM8)
-16-bit up, down, up/down auto-reload counter.
-Used for 3-phase motor control.
Basic timers (TIM6&TIM7)
- 16-bit auto-reload upcounter.
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32. Timers configuration Timer clock configuration: HCLK = SYSCLK
PCLK1 = HCLK / 4
TIM_CLK = 2*PCLK1 = SYSCLK / 2
To configuring Timers using SPL driver:
Include stm32f4xx_tim.h;
Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function;
Fill the TIM_TimeBaseInitStruct with the desired parameters;
Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit with the corresponding configuration;
Enable the NVIC if you need to generate the update interrupt;
Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update);
Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
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33. Interrupts and events Nested vectored interrupt controller (NVIC)
The nested vector interrupt controller NVIC includes the following features:
• 82 maskable interrupt channels for STM32F407xx;
• 16 programmable priority levels (4 bits of interrupt priority are used);
• low-latency exception and interrupt handling;
• power management control;
• implementation of system control registers;
The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of up to 23 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests.
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34. CMSIS NVIC driver Definitions: misc.h
Interrupt table: startup_stm32F4xxx.s
Define your interrupt handler;
Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig();
Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() .
Example:
NVIC_InitTypeDef nvic_struct;
nvic_struct.NVIC_IRQChannel = TIM2_IRQn;
nvic_struct.NVIC_IRQChannelPreemptionPriority = 0;
nvic_struct.NVIC_IRQChannelSubPriority = 1;
nvic_struct.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&nvic_struct);
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35. Is there any questions?
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36. Thank you! COPYRIGHT © 2016 DSR CORPORATION36