1. Embedded Design with the Xilinx Embedded Developer Kit

2. Welcome
If you are new to Embedded design with Xilinx FPGAs, this module will help you start planning your design
Understanding the difference between Xilinx’s FPGA architectures is essential if you are going to select an appropriate FPGA device family
The Embedded Developers Kit software (EDK) is designed to make building a custom embedded design easy

3. After completing this module…
…you will be able to:
Choose between a PPC 440 and a MicroBlaze processor system
Explain the primary tool functionality included with the Embedded Developers Kit (EDK)
Explain the benefits of building an embedded design with an FPGA

4. Lessons Hardware Introduction Overview of EDK
Embedded Development Design Flow
Summary

5. Xilinx Embedded Processor Innovation
PowerPC 440
Embedded Block with Integrated Interconnect
Performance
Integration
Flexibility
Features
PLB Embedded Development Kit IP
PowerPC 405
Hard Core
in Virtex-4 FX FPGA
PowerPC® 405
Hard Core
in Virtex®-II PRO FPGA
32-bit RISC
Processor
Soft Core
2000
2002
2004
2008
2006

6. Supported FPGAs FPGA families
Spartan-3/3A/3AN/3A DSP/3E FPGA (MicroBlaze processor)
Spartan-6 (MicroBlaze Processor)
Virtex-4 FX (MicroBlaze and PowerPC 405 processors) and LX/SX FPGA (MicroBlaze processor)
Virtex-5 FXT (MicroBlaze and PowerPC 440 processor) LX/LXT FPGA (MicroBlaze)
Virtex-6 (MicroBlaze processor)

7. Embedded Design in an FPGA
Embedded design in an FPGA consists of the following
FPGA hardware design
Processor system
MicroBlaze processor (soft core)
PowerPC processor (PPC440 hard core)
PLB bus components
Other FPGA hardware
Software platform for processor system
Standalone
C language support
Processor services
C drivers for hardware
Third-party operating systems (optional)
User software application
Typically the FPGA contains logic that can be unrelated to the processor component of the design. This is part of the system-on-chip or single chip architecture concept.
Xilinx can support multiple processor instances. Each processor instance will have its own software platform that may or may not include a third-party operating system, such as Linux, or one of the many Real-Time Operating Systems (RTOS).
A software platform that does not include an OS will use the Xilinx Standalone platform that provides the basic software services.
The user software application is written from the aspect of main and performs the desired function.
Interrupt service routines may be part of the user application.

8. PowerPC Processor-Based Embedded Design
440 Core
Dedicated Hard IP
MCI
DMA
PPC DDR2 Memory Controller
DDR
TEMAC
MPLB
SPLB
PLB v46
PLB v46
The PPC 440 is integrated into the silicon of the FPGA. It interfaces with the outside world via a crossbar technology that consists of the following interfaces.
Memory Controller Interface (MCI): The PPC 440 processor supports an MCI port that is designed to connect directly to the PPC processor DDR2 memory controller. The separate memory interface improves system performance and enables access to larger memories.
Direct Memory Access (DMA): The PPC 440 processor also has four DMA ports. These are commonly used to connect to the tri-mode Ethernet MACs included with the Virtex-5 FPGA.
Processor Local Bus v46 (PLB v46): The PLB v46 interface supports a bus width of up to 128 bits of data. The PPC 440 processor supports both a master and two slave PLB v46 buses. The master bus allows the PPC 440 processor to access any PLB v46 peripherals placed on it while the slave bus allows other masters (on the slave PLB bus) to access MCI memory and the master PLB v46 bus. The PLB v46 supports dynamic bus sizing as well as programmable burst size.
e.g.
Memory
Controller
Hi-Speed
Peripheral GB
E-Net
UART
GPIO
Bus
Master
Off-Chip
Memory
Full system customization to meet performance, functionality, and cost goals
ZBT SSRAM
DDR SDRAM
SDRAM

9. MicroBlaze Processor-Based Embedded Design
I-Cache
BRAM
Local Memory
Bus
MicroBlaze
32-Bit RISC Core
Flexible Soft IP
BRAM
Configurable
Sizes
D-Cache
BRAM
Possible in
Virtex™-5 FXT
PowerPC
405 Core
Dedicated Hard IP
PowerPC
405 Core
Dedicated Hard IP
Dedicated Hard IP
Dedicated Hard IP
PowerPC
PowerPC
405 Core
440 Core
Fast Simplex Link
SPLB
PLB v46
0,1….7
MPLB
Custom
Functions
Custom
Functions
PLB v46
Hi-Speed
Peripheral GB E -
Net
UART
Memory Controller
Because the MicroBlaze processor is a soft-logic processor, it runs on all current FPGA families.
Local Memory Bus (LMB): The MicroBlaze processor has a 32-bit LMB that is used for low-latency access to on-chip block RAM. The LMB provides single-cycle access to on-chip, dual-port block RAM and is split into instruction-side LMB and data-side LMB.
Off-Chip Memory Caches: Off-Chip memory is accessed via the PLB v46 bus. A configurable option will let you add instruction and data caches and configure their sizes. Caches are implemented with FPGA block RAM. The MicroBlaze processor includes a tightly coupled, off-chip Flash/SRAM memory controller interface to provide high-speed, low-latency access, called CacheLink. The CacheLink interface implements the cache function without tying up the PLB v46 bus. This is similar to the Fast Simplex Link (FSL).
Fast Simplex Link (FSL): The MicroBlaze processor contains zero to sixteen input and output Fast Simplex Link interfaces. The FSL channels are dedicated, unidirectional, point-to-point data-streaming interfaces. The FSL interfaces on the MicroBlaze processor can be up to 32 bits wide. In addition to the data, an additional control bit is implemented that can be sensed as a MicroBlaze processor condition code. There are eight cycle-assembly instructions that implement register-to-FSL operations. Wrapping this into custom C functions provides an optimal method by which you can implement custom instructions to a hardware co-processor function.
PLB v46: The MicroBlaze and PPC 440 processors both use the PLB v46 bus. The same peripherals that work on the PLB v46 with the PowerPC processor can also be used with the MicroBlaze processor.
PowerPC processor: Xilinx allows multiple processor instances. In this figure, both processors have been connected to the same slave PLB v46. This allows less critical functions to be ported off to the MicroBlaze processor and the most timing critical to be ported to the PowerPC processor on the master PLB v46 bus. In this particular scenario, the MicroBlaze processor will have access to PowerPC 440 processor MCI memory and the MPLB peripherals.
CacheLink
Off-Chip
Memory
SRAM
FLASH/SRAM

10. IP Peripherals All are included FREE!
Bus infrastructure and bridge cores
Memory and memory controller cores
Debug
Peripherals
Arithmetic
Timers
Inter-processor communication
External peripheral controller
DMA controller
PCI
User core template
…and Other cores
Bus infrastructure and bridge cores
Fabric Co-processor Bus (FCB)
Fast Simplex Link (FSL)
DCR bridge and bus
PLB v46 to PLB v46 bridge
Local Memory Bus (LMB) (MicroBlaze processor)
Memory and memory controller cores
Block RAM (PLB v46/LMB)
PPC 440 DDR2 memory controller
Multi-port memory controller (SDRAM, DDR, DDR2)
Multi-channel external memory controller (SRAM, FLASH)
System ACE™ interface controller (Compact Flash)
Debug
ChipScope™ Pro tool (ILA, controller, PLB v46)
MicroBlaze Debug Module (MDM)
PPC JTAG controller
Peripherals
SPI interface, UART, UART lite
Hard-core tri-mode Ethernet MAC
10/100 Ethernet MAC

11. Lessons Hardware Introduction Overview of EDK
Embedded Development Design Flow
Summary

12. Embedded Development Kit
What is the Embedded Development Kit (EDK)?
The Embedded Development Kit is the Xilinx software suite for designing
Complete embedded programmable systems
Processor sub-system component of larger design
The kit includes all the tools, documentation, and IP that you require for designing systems with embedded IBM PowerPC 440 hard processor cores and/or Xilinx MicroBlaze soft processor cores
SDK Eclipse-based software design environment
It enables the integration of both hardware and software components of an embedded system
For a list of currently supported operating systems and system requirements for both the EDK and ISE® software, go to

13. XPS Functions Software application management Platform management
Software library generation (LibGen)
Software Profiling
Xilinx Microprocessor Debugger (XMD) and Software Debugging
Xilinx MicroKernel (XMK)
Platform management
System create wizard (BSB)
Netlist Generation (PlatGen)
Custom Peripheral creation wizard
Hardware Debugging (ChipScope)
Hardware Simulation (SimGen)
Hardware
Design
XPS
HW/SW
Simulation
The Xilinx Platform Studio (XPS) GUI provides a central platform to manage the hardware design on the processor system component and any custom peripherals that you may design. From XPS, you can launch tools that will perform the following.
Hardware design
Processor and Xilinx-provided peripherals
Custom peripherals
Netlist generation
Software design using SDK
Software platform generation
User application
Hardware/software simulation
Simulation HDL model generation
Bus Function Model (BFM) generation for PLB v46 bus peripherals
Instruction Set Simulator (ISS)
Hardware/software debug
ChipScope Pro tool for hardware
XMD/GDB for software using SDK
Software
Design - SDK
HW/SW
Debug

14. Xilinx Platform Studio (XPS)
See the Notes section for a detailed description
Connectivity
Panel
Project
Information
Area
System
Assembly
View
IP Catalog Tab:
The IP Catalog tab opens lists all the EDK IP cores as well as any custom IP cores that you created. If a project is open, only the IP cores compatible with the target Xilinx device architecture are displayed.
The catalog lists information about the IP cores, including release version, status (active, early access, or deprecated), lock (not licensed, locked, or unlocked), processor support, and a short description.
Additional details about the IP core, including the version change history, data sheet, and Microprocessor Peripheral Description (MPD) file, are available via right-click.
By default the IP cores are grouped by function.
System Assembly View:
The System Assembly view is always displayed when an XPS project is open, and it closes when the project is closed. This view allows you to view and edit your hardware platform.
Select the Bus Interface, Ports, and Addresses tabs to view the corresponding aspects of your design. The default is Hierarchical view, in which the information for your design is grouped into a tree by the IP core instances in your hardware platform.
The Expand All Tree Nodes and Collapse All Tree Nodes tool bar buttons at the top of the pane allow you to expand and collapse all the nodes in the IP instance tree. You can also expand and collapse an individual tree node by clicking the +/- sign next to it.
The Flat View toolbar toggle button allows you to display the information with or without the IP core instance tree. In the flat view, you can sort the table alphanumerically by any column.
Connectivity Panel:
The Connectivity Panel is part of the System Assembly view when the Bus Interface tab is selected. This panel is a graphical representation of the bus connectivity of your hardware platform.
Each vertical line represents a bus, and each horizontal line represents the bus interfaces for an IP core. A connector is displayed at the intersection if a compatible connection can be made between the bus and IP core bus interfaces.
The lines and connectors are color-coded to show compatibility.
The different shapes of the connections symbolize the mastership of the IP core bus interface. A hollow connector represents a potential connection that you can make, and a filled connector represents a connection that has already been made.
To make or disconnect a connection, click the connector symbol.
Console

15. Quiz1_MB

16. Lessons Hardware Introduction Overview of EDK
Embedded Development Design Flow
Summary

17. Embedded Development Design Flow1
Create a new EDK project
Use the Base System Builder (BSB) to construct your basic embedded design
Run PlatGen to make your HDL instantiation files and netlist for each component in your embedded design
Implement the embedded design with the ISE software
Create and compile your software with SDK
Merge your compiled software with the FPGA bitstream using the Data2MEM utility
Download your FPGA’s completed bitstream using iMPACT 2 3 4 5 6 7
Note that this is simplified development process. The complete process includes enabling hardware simulation, software debugging, construction of custom peripherals, integration of IP with the IP wizard, and software optimization.

18. Launching a New XPS Project
It is recommended that XPS processor projects be launched from Project Navigator in the ISE software
Easy to integrate a processor sub-system with other FPGA logic
Access to more Xilinx point tools
Easy software integration
The processor sub-system can be placed anywhere in the design hierarchy
More on this in later modules
There is an alternate design flow where the entire design is performed in XPS. This flow is only used if the processor system is the only component on the FPGA. It offers one stop shopping in that all development tools are accessed from XPS.
This flow is simpler to use than the ISE tool/XPS flow and is often a preferred alternative when prototyping processor-only designs on evaluation boards.

19. Starting out with a Processor Design
Many vendors support evaluation and demo boards with Xilinx FPGAs
Xilinx
Avnet
NuHorizons
Digilent
Base System Builder (BSB) is a wizard to facilitate a fast processor-based system design by high abstraction, level-specification entry
Virtex®-5 FPGA ML507
Spartan®-3E FPGA 1600E

20. Project Creation Using the Base System Builder
Select a target board
Select a processor
Configure the processor
Select and configure I/O interfaces
Add internal peripherals
Generate system software and a linker script
Generate the design
Generated files include the following
system.mhs
system.xmp
data/system.ucf
pcore directory (empty)
Select a development board by choosing a vendor, a board name, and a revision. A brief description of the selected board shows the Xilinx FPGA device and a list of standard I/O devices on the board. BSB recognizes boards through Xilinx Board Description (XBD) files supplied by the board vendors.
2. Select either the MicroBlaze soft processor or PowerPC 440 processor. Note that the BSB will only allow you to target the PowerPC processor if a supported device is selected. BSB also shows a typical system diagram and a brief description of the processor, based on your selection.
3. You can configure the processor system that you just selected, including operating clock frequency, debug interface, and on-chip memory configuration. Click More Info to see a detailed explanation of each feature.
Select and configure the I/O interfaces to other devices connected to the Xilinx FPGA. Deselect the interfaces that you do not want to include in your system. Then, for those interfaces in the system, select the Xilinx cores that communicate with the corresponding I/O devices. For each selected core, the number of parameters is kept to the minimum to ensure ease-of-use by using fixed settings from the board description file and intelligent defaults. You can change and override any setting in XPS after BSB finishes.
Upon completion, the BSB generates a memory map for the entire system and adds the necessary files under your project directory.
Some of the files generated include:
system.mhs and system.mss: Hardware and software description files. The system.mhs file contains your finished hardware design. The system.mss is the software netlist that matches software system services and drivers to each of the hardware components.
data/system.ucf: Xilinx user constraint file, which contains timing constraints and pin assignments.
etc/fast_runtime.opt: Xilinx implementation options setup file for implementing the design with the ISE tools when the design flow is performed in XPS as opposed to an ISE generated processor system design.
etc/download.cmd: Xilinx download command file, which XPS uses to automatically initialize the BSCAN chain when downloading to hardware (XPS flow only).

21. Generating the Processor Hardware Netlist
Select Hardware  Generate Netlist
Platform Generator: PlatGen
Input file  MHS and MPD
The MHS file defines the configuration of the embedded processor system, including the bus architecture, peripherals and processor(s), interrupt request priorities, and address space
The MPD file defines the configurable parameters with their default values and available ports for a peripheral
Output files  system netlist, peripheral netlists, and BMM file
Creates the synthesis, HDL, and implementation directories
Generates the HDL wrapper files for the peripherals
Generates the top-level system HDL file
Extracts the peripheral netlists from the EDK install directory
Generates the BMM file
Calls XST to synthesize the top-level wrapper file
The Microprocessor Hardware Specification (MHS) file is the heart of the processor system design. It is a netlist of the processor system components and their connectivity. The file is written in a proprietary format and stored as ASCII text. With this file and the XMP project file, an entire EDK hardware design can be defined and recovered.
The System Assembly view in XPS is basically a graphical editor for the MHS file. It saves the designer from being an expert in the MHS component and file descriptions.
The MHS file defines the configuration of the embedded processor system and includes the following:
Bus architecture
Peripherals and processor(s)
Interrupt request priorities (if necessary)
Peripheral address space assignment
Peripheral options
Clocking, debug, and reset components
External ports of the processor system
The Microprocessor Peripheral Definition (MPD) file defines the interface of the peripheral. An MPD file has the following characteristics:
Lists ports and default connectivity for bus interfaces
Lists parameters and default values
Simulation model options
The parameters assignment listed in the MHS file overwrites corresponding parameter values in the MPD file.

22. Detailed EDK Design Flow
Standard Embedded Software Flow
Standard Embedded Hardware Flow
Source Code
(C code)
MHS File
system.mhs
Source Code
(VHDL/Verilog)
Compile
Processor IP
MPD Files
PlatGen
Synthesis
Object Files
LibGen
EDIF
IP Netlists
Link
Libraries
system.ucf
FPGA Implementation
(ISE/Xflow)
Executable
Data2MEM
Create FPGA Programming
(system.bit)
The hardware platform is defined by the Microprocessor Hardware Specification (MHS) file (this is the primary output file from the BSB). The MHS file defines the system architecture, peripherals, embedded processors, connectivity of the system, address map of each peripheral in the system, and configurable options for each peripheral. The System Assembly view is the graphical editor for the MHS file.
The Platform Generator tool creates the hardware platform by using the MHS file as input. PlatGen creates netlist files (NGC), support files for downstream tools, and top-level HDL wrappers that allow you to add other components to the automatically generated hardware platform. This tool is invoked via Hardware  Generate Netlist.
After PlatGen runs, FPGA implementation tools (the ISE software) are run to complete the implementation of the hardware. At the end of the ISE software flow, a bitstream (system.bit) is generated to configure the FPGA. This bitstream includes block RAM initialization information (if block RAM is used).
If user software code or data is required to be placed on these memories at startup time, the Data2MEM tool in the ISE software toolset is used to update the bitstream with code and data information obtained from your executable ELF, which is generated after your software has been compiled. The updated bitstream generated with your user software application information is called the download.bit file.
download.bit
Hardware

23. Software Flow
Software development is performed with the Xilinx Software Development Kit (SDK)
A hardware image XML file must first be generated to define the hardware platform for which the software application will be developed
The SDK software tools will then attach the software project to the hardware
SDK can be launched now or later, Export Only
The software platform or board support package is generated by the SDK software design environment when SDK is first launched. The software platform is based on the hardware makeup of the processor system.
SDK identifies the hardware configuration from a hardware description in the XML file. The XML file is generated in XPS in the Export to SDK process.
You have a choice of exporting and launching SDK if want to begin software development now, or just export and launch SDK at some later time. If the hardware changes, it is necessary to Export to SDK again.

24. SDK Software Development
Create software platform
System software, board support package
LibGen program
Create software application
Create Linker Script
Build project  compile, assemble, link
Output file  executable.elf
The SDK is the software design environment tool of EDK. EDK allows hardware development in XPS and independent software development using SDK.

25. Merging Hardware and Software Flows
Data2MEM
FPGA Partial Reconfiguration enables the reprogramming of the Block RAM contents without reprogramming the entire FPGA
Saves download time
Saves re-implementation time
Enables software debugging
Use of off-chip RAM encouraged for large pieces of software (typical)
download.bit
MicroBlaze/ PPC
UART
Arbiter
GPIO
When the program code is executing from block RAM, it is loaded directly into the bitstream by the Data2MEM program. This facilitates keeping the hardware and software designs somewhat independent so that if one or the other changes, it is not necessary to re-implement the hardware or re-compile the software.

26. Configuring the FPGA Download the bitstream Accessible from all tools
Input file  download.bit
This downloads the download.bit file onto the target board by using the Xilinx iMPACT tool in batch mode
Accessible from all tools
XPS
SDK
Project Navigator
Requires that the download cable is connected
SDK
XPS
The FPGA is typically configured using the download cable during the project design phase. This service is available from all design flows.
The XPS flow is used when the processor system is the only hardware in the FPGA.
Use the SDK flow when the hardware is stable and the software is changing.
Use the ISE tool flow when the software is stable, but other hardware, unrelated to the processor design, is changing.
In any event, make sure you are using the BIT file that was loaded with the ELF object code file; otherwise, you may be attempting to execute a non-existent program from a BIT file that has no program object code in its block RAM locations.
ISE Tool

27. Virtex-5 FPGA ML507 Lab Board
RS-232 cable – transmits serial information from your PC to your embedded system (the other end is attached to the PC). A null modem is needed.
If your machine is equipped with an RS-232 serial communications port, then a straight-through DB-9 to DB-9 cable is required. Many desktop machines still have this port. If you use a laptop, most of which do not contain RS-232 ports, you will need an RS-232 to USB adapter.
You will also need a null-modem connector for the ML507 board as it only supports a DTE RS-232 connection.
High-performance ribbon cable
Xilinx USB platform cable – configures the FPGA (the other end is attached to the USB port of the PC)

28. Demo Boards Spartan-6 FPGA LXT SP605 MicroBlaze Development Board
Virtex-5 FPGA FXT ML507 PowerPC Evaluation
Platform
Spartan-3E FPGA XC3S1600E
MicroBlaze Development
Board
Labs for this course use the Spartan-6 FPGA SP605 Evaluation Kit, Spartan-3E FPGA Embedded Processing Development Kit, or the Virtex-5 FXT FPGA ML507 Evaluation Platform. For information on additional development platforms, go to > Products & Services > Boards & Kits.
Lab instructions are provided for both the PowerPC 440 and MicroBlaze processors

29. Lessons Hardware Introduction Overview of EDK
Embedded Development Design Flow
Summary

30. Quiz_final_MB

31. Summary
The Embedded Development Kit (EDK) includes all the tools, documentation, and IP necessary for building embedded systems
The Software Development Kit (SDK) is a comprehensive software development environment for simple software and firmware for complex applications
The Base System Builder (BSB) makes it easy to build a full hardware design targeting an available demo board
Merging software into an FPGA hardware bitstream is completed with the Data2MEM utility (Update Bitstream)
Hardware netlists for an embedded design are implemented with the ISE tools

32. Where Can I Learn More? Xilinx Embedded Processing page
Learn more about Embedded Design Kits for all Xilinx product families
Xilinx online documents
Getting Started with the Embedded Development Kit
Processor IP Reference Guide
Right-click any peripheral from the IP Catalog to learn more about it
Embedded Systems Tools Guide
Xilinx Drivers
Processor reference guides
PowerPC 405/440 Processor Block Reference Guide
MicroBlaze Processor Reference Guide
For all docs, select Help  EDK Online Documentation from the EDK tools

33. Where Can I Learn More? Xilinx Training Courses
Embedded Systems Development course
Rapidly architect an embedded system
Introduction to most of the EDK tools
Embedded Systems Software Development course
Rapidly architect an embedded software system
Introduction to the SDK (Software Development Kit)
Advanced Embedded Systems Development course
Take advantage of advanced features of the PPC440
Apply advanced debugging techniques including ChipScope
Design a Flash memory-based system and boot load from off-chip Flash memory
Customers spend 50% of their time in lab

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Embedded Design with the MicorBlaze Soft Processor Core
Embedded Design with the PPC 440

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