1. Actel Fusion PSC: The World’s First Mixed-Signal FPGA Rich Howell, Product Marketing Manager Martin Mason, Director, Silicon Product Marketing Dennis Kish, VP, Marketing John East, CEO Embargoed until December 12 th 2005

2. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 2 Actel Company Overview  Established FPGA Supplier  First product shipped - 1988  $166M in sales in 2004  59 consecutive quarters of Pro Forma profitability  Strong balance sheet $153M cash, no debt  More than 550 employees  Fabless company  #1 flash FPGA supplier  #1 antifuse FPGA supplier  100% green and RoHS compliant

3. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 3 The Challenges Facing Today’s Designer Time to market and design costs driving Programmable System Chip (PSC) market Analog Suppliers FPGA Suppliers cin >>X >>Y; for (;;) {cout <<" X,Y=?"; cin >>X>>Y; } MCU Suppliers ASIC Suppliers LUT Programmable System Chip

4. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 4 The Solution: Actel Fusion PSC  Changes the competitive landscape  The world’s first mixed-signal FPGA  Fusion unlocks creativity: New architecture provides configurability and new tools provide simplified design flow Typical System MPU / MCUFPGA / ASIC Power Mgmt System Memory DRAM NV Storage FLASH Clock Mgmt Analog Interface Cache Memory SRAM Discrete Analog

5. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 5 Fusion Configurability Benefits  Late-stage manufacturing and secure field updates through ISP of FPGA fabric: Up to 1.5M system gates  Single update for firmware (flash) and hardware  Single chip, many projects  One-stop shop and economies of scale  Market-specific customization  High precision with on-the-fly analog dynamic range selection  Power optimization through multiple configurable clocks sources and PLL  Configurable peripherals provide ultimate soft MCU platform

6. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 6 Fusion PSC: Changing the Competitive Landscape Highly Integrated Application Optimized Secure Low Power Live at Power-up On-chip Flash Low Unit Cost Monolithic Nonvolatile Analog No NRE Configurable Rapid Prototyping Short Lead-time ISP Extendable/Flexible FPGA ASSP or Mixed-Signal ASIC

7. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 7 Unlocking Creativity: A New Architecture for System Design  Interface to the real world  Analog inputs ±12V  Temp, current, voltage sensing  ADC – up to 600KSPS, up to 12 bits  High current outputs (PWM / FET)  5V digital input support  Simplifies system initialization  Live at power-up  Monitor and sequence power supplies  ‘System Boot code’ flash storage  Flexible clock resources  100MHz RC oscillator  32kHz to 20MHz Xtal OSC  Portable ready  Low power (static and dynamic)  State saving low power sleep mode  RTC – for periodic wake-up  Integrated, single chip  Flexible flash  Flash: x8, x16 or x32 interface  EEPROM emulation  Up to 100MHz access GPIO FLASH Memory Analog Inputs MOSFET Outputs A/D Ana Mux JTAG Port Mux A3P FPGA Fabric (incl. SRAM, CCC/PLL, IO) Xtal OSC, RC OSC, RTC, Vreg

8. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 8 Fusion Family

9. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 9 Fusion PSC: Target Applications  Power and temperature management  Power sequencing with tracking control  Smart battery charging  Voltage, current, temperature monitors and alarms  Fan and heat-element control and monitoring  Intelligent Platform Management Interface (IPMI)  Motor and motion control  Motor control – stepper, 3-phase and solenoid control  Anti-lock brakes  System initialization and configuration  Context save and restore  Context switching  System boot codes  Storage  Program code storage  EEPROM emulation  Data acquisition and logging  Low power and clocking  Control for sleep mode and wake-up  Live at power-up clock generation, conditioning, and distribution

10. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 10 Fusion Flexibility: Power Management Applet Everything today’s system sequencers can do plus…  FPGA gates – your design here…  Event and alarm logging using on-chip flash for remote diagnostics  Sequence system along with power management activities  Enable devices, system buses, interfaces, memories etc. during power-up/down  Additional system management activities: Thermal monitoring and fan control  Easy field changes of sequences or alarm levels use Fusion flash  Upgradeable using spare I/Os and gates  Support for ANY voltage from ±12V  High precision through infinite supply ramp control  No compromises

11. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 11 Typical System Board Before Fusion Temp Monitor and Fan Cntrl Processor Digital FPGA EEPROM Power Seq. Current Monitor and Brown-out detect RTC RTC to track real time and time stamp events Thermal mgt IC for fan control Clock chip require because FPGA has no source OSC. Clock Chip External flash for code Sequences and monitors multiple power supplies ADC ADC to interface to “real world” E 2 PROM for data logging Memory NV Storage PWM For motor control CPLD CPLD for SRAM configuration /supervisory

12. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 12 Typical System Board After Fusion Processor Memory FUS1ON PSC

13. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 13 Fusion Integration Reduces Cost 4M EEPROM (industry ASP)$5.20 4M Flash (industry ASP)$0.65 Power-up Seq/FET Drivers (LSCC, Summit)$8.00 OSCs/PLLs/Clock Buffs/Roboclocks (CY)$5.00 Temp monitors/Fan control (ADI)$4.00 Voltage/current monitors (LTC–3ch)$2.10 Comparable ADC (Maxim)$2.50 Real time clock (Maxim)$1.30 Configuration PROM$2.00 LAPU CPLD$1.00 Total Savings $31.75

14. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 14 Fusion Stack: Simplifies Design  Level 0 - Fusion smart peripherals  Peripherals are treated equally, whether hard-wired or soft IP  Level 1 - Fusion Smart Backbone  Built-in control (soft IP) configures peripherals from flash memory  Backbone is scalable to any number of peripherals or applets  Level 2 - Fusion applets  Application building blocks implementing specific functions  Rapid deployment  Applets can be rapidly combined to create large applications  Level 3 - User application  Optional ARM7 or 8051  Verified and integrated (CoreConsole)  Well-defined interface for external IP and tool integration FPGA Fabric User Application Optional MCU (ARM or 8051) Flash Memory ADC Analog I/O OSCs, RTC Fusion Applet 2 (i.e. Thermal Mgmt) Fusion Applet 1 (i.e. power sequence) Fusion Applet 3 Fusion Smart Backbone Control

15. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 15 A complete design in three clicks New Tools: CoreConsole IP Deployment Platform  Click - Add parts  Add IP to design from list of available IP  Click - Design  Configure and stitch IP  Can be done in design or schematic window  Click - Generate  Generates IP (design) RTL and other output items (test benches, etc.)  SPIRIT supported  Structure for Packaging, Integrating and Re-using IP within Tool flows (SPIRIT)

16. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 16 New Tools: SmartGen Peripheral Configurator  New graphical productivity tools  ADC sampling  Digital low-pass filtering  Threshold comparisons  State filtering  Analog input  High current output  Flash memory access (FlashPoint™)  Automatically connects FPGA, flash and analog to Smart Backbone

17. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 17 On Dec. 12 th Actel Will Announce…  Silicon samples - now  AFS600 available now  Fusion from $4.95 (250KU 2H 2006)  Software tools - now  Libero v7.0 IDE shipping now  Fusion Smart Backbone  Free IP with Libero  Hardware tools - now  Shipping now  Starter Kit ($349)  Libero IDE Gold  Fusion evaluation board  FlashPro3  Tutorial and documentation  Logic Navigator debugger

18. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 18 Actel Fusion PSC  Changes the competitive landscape  Fusion unlocks creativity: New architecture provides configurability and new tools provide simplified design flow  The world’s first mixed-signal FPGA and the ultimate Programmable System Chip  Replaces costly and time-intensive alternatives  Mixed-signal ASIC / ASSP  Discrete FPGA with analog, CPLD+

19. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 19 Forward-looking Statement  All forward-looking statements are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Actual results may differ materially from those forecast in the forward- looking statements for a multitude of reasons, including the “Risk Factors” set forth in Actel’s most recent Form 10-K or 10-Q, which can be found on Actel’s Web site, www.actel.com  Unless the context otherwise requires, all statements are made as of the date indicated. Actel undertakes no obligation to update any statement, including any forward-looking statement.

20. Appendix

21. © 2005 Actel Confidential and ProprietaryEmbargoed Until December 12, 2005Actel Fusion Programmable System Chip 21 Fusion Chip PA3 Digital I/O User FROM Security FPGA Core SRAM / FIFO PLL/CCC Charge Pumps Embedded Flash Analog – to – Digital Converter Analog Inputs Gate Drivers Clocking RTC, Xtal Osc.