1. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 1 Trigger-Region-Unit for PHOS Calorimeter H.Muller, R.Pimenta, D.Rohrich, B. Skaali, A.Oltean 1.PHOS in Alice Detector 2.Detector Components 3.Single Crystal Readout 4.Crystal Strip Units 5.FEE and TRU Packaging 6.Trigger Region 13. Serial ADC Interface 14. Oversampling 15. 480 Mb/s Deserializer 16. Level-0 Timing 17. Trigger Output at 40 MHz 18. TRU Card Status 7.Front end Electronics (FEE) 8.Fast OR 9.FEE  TRU Connectivity 10.Trigger Tasks 11.Analog-Digital Conversion 12.Signal Routing Implementation TRU General PHOS Trigger approach

2. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 2 PHOS in Alice Detector Single PHOS Module: 56 * 64 PWO crystals Alice Detector PHOS detector: 5 modules cover 5*20 degrees 18.000 PWO crystals 36.000 readout channels Level-0, Level-1 Trigger Electromagnetic Calorimeter ( photons and electrons) resolution goal is 3.5 % @ 1 GeV

3. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 3 Detector Components Synthetically grown PWO crystal PHOS crystal cutout, polished APD (Hamamatsu 5mm 2 ) CSP preamplifier (FET based) one of 18.000:

4. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 4 Single Crystal Readout T-card Charge sensitive preamplifier (CSP) 1 Volt/pico-Coulomb (APD on backside) Photo of 1 assembled detector

5. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 5 Crystal Strip Units ( inside 1 module) Double Strip Unit for 2*8 Crystals Left-Right orientation of 2 Double Strip Units = 1 FEE card (plugged below) L R FEE card

6. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 6 FEE and TRU Packaging (fully embedded and water cooled) TRU cards 1 TRU region 14 FEE cards FEE cards Conceptual: Technical:

7. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 7 Trigger Region 7 FEE cards TRU card 64 crystals ( 20 degree sector) TRU region 3584 crystals 8 TRU domains 16 28 56 crystals One TRU region Fast OR cables from FEE to TRU 1 TRU = 448 (16 x 28) crystals 1 PHOS module (8 TRU) = 3584 (64 x 56) crystals PHOS module

8. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 8 Front End Electronics FEE card properties 32 ch. dual gain shapers 32 APD bias regulators 4 x 10 bit ADCs (Altro) RMS noise 0.4 ADC counts 14 bit dyn range 5 MeV–80 GeV Fast OR (2*2 ) for trigger Board controller (PCM) USB controller for tests GTL+ readout bus (TPC) Readout via RCU (TPC) 5.5 Watt, 349 * 210 mm 2 32 channel Front-End Electronics card

9. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 9 Fast OR (FEE output) >95% of light in < 40 ns Saturation at 32 GeV Fast OR latency relative to preamplifier ~ 75 ns L0 trigger based on 100 ns charge signal Copy CSP preamplifier signals into a fast shaper (100 ns) Analog output: charge sum of 2* 2 crystals

10. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 10 FEE  TRU Connectivity Overview TRU 8 112 analog inputs from 14 FEE cards Level-0 Level-1 Crystals/DetectorAnalog/Digital ElectronicsTrigger Generation

11. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 11 Trigger Tasks (implemented in Xilinx FPGA) Level-0 Decision latency: 800 ns pre-trigger for Level-1 use only low-bit threshold Level-1 Decision latency: 5 us high p T photons Pb+Pb use only high-bit thresholds 1.Level-0 ( FPGA Algorithm stage 1 ) –sum up neighboring cells in space ( 4*4 cells) –sum up analog Fast OR signal in time (100 ns) –trigger if space-time sum is bigger than threshold –detect signal peak in phase with 40 MHz –output L0 trigger as 40 MHz NRZ signal 2. Level-1 ( FPGA Algorithm stage 2) Only if level-0 has triggered: –determine space-time sum above 3 higher thresholds ( low, mid, high p T ) –send triggers to 3 outputs (low, mid, high) –store triggers in hit memory –trigger after max. 5 us

12. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 12 Analog-Digital Conversion ( 112 analog inputs on TRU)

13. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 13 Signal Routing (differential LVDS 480 Mb/s) ADCs, length adjusted routing Xilinx Virtex-II Pro FPGA ( 1152 BGA) One side of Allegro routing Difficulty: 112 differential signals of fixed polarization from ADC at controlled impedance

14. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 14 Serial ADC Interface (112 LVDS interfaces @ 480 Mb/s) Original Problem: –Build 14 interfaces inside the FPGA (Xilinx Virtex-II Pro) for processing the 112 inputs (480Mb/s) from the ADS devices State of Art approach: –Standard solution (Xilinx AN - xapp774) for connecting one ADS527X to XV2P50 does not work in our case –This solution uses one Digital Clock Management (DCM) block per ADS interface –But: our design would need 14xDCMs for 14 different ADS interfaces and only 8xDCMs are available in the XV2P50 Proposed solution: –As a replacement for DCM use oversampling at 1.44GS/s to align the 112 DDR with 240 MHz high-speed clock –DeSerialize 112 DDR after oversampling and output the parallel data –Special attention given to constrain the interface design: maximum skew less than 300ps, equal delays for all inputs, area groups inside the FPGA

15. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 15 Oversampling DATAIN Serial DDR from ADS5270 (running at 240MHz) Oversample and Shift DATAIN in 3 stages (1.44GS/s) Align output to positive and negative edge of 240MHz clock ff_*_1ff_*_2 1 st stage2nd stage3rd stage DATAIN D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q Clk240_0 Clk240_60 Clk240_0 Clk240_60 Clk240_0 Clk240_60 Clk240_120 Clk240_180 Clk240_240 Clk240_300 Sync to clk240_0 Sync to clk240_0 DataIn_P DataIn_N Sel_P[1:0] Sel_N[1:0] DMUX_N DMUX_P

16. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 16 DatOut[11:0] EnaMux DataIn_P D Q5 Q4 Q3 Q2 Q1 Q0 E Flip-Flop Cascade Q Q Q D EnaRegClk0 Flip-Flop Cascade Q Q Q D D Q5 Q4 Q3 Q2 Q1 Q0 E EnaRegClk180 Data Multiplexer D Q D Q Clk240_0 Clk240_180 Data[0:11] DataIn_N DeSerializer ( LVDS input @ 480 Mb/s to 12 bit register ) Input data DataIn_P and DataIn_N aligned in the oversampling module Deserializer 2 FF cascades for even and odd bits 2 parallel registers, clocked on the positive and negative edge of 240Mhz clock Multiplexer used to align (swap if necessary) odd and even bits in the final 12-bit register Output data 12-bit parallel data DataOut[11:0]

17. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 17 Level-0 Timing Interaction time t=0 12 bit ADC (28ns) Central Trigger max. 800 ns (L0) ~ 40 m = 200 ns fixed delay FPGA 40 MHz Level-0 FPGA Process : 112 @ 40 MHz synchronous pipelined space-time summing and threshold compare Available time in the FPGA: maximum 440 ns ~ 200 ns DeSer (25ns) ( 20ns) ( 20ns) (10 ns) (80 ns) TOF shower APD analog Sum ~ 350 ns Analog  Digital peak thresh. compare ~ 400 ns NRZ pipeline 4-deep time summing 25 ns 40 MHz 40 MHz NRZ serial Trigger 4*4 space Sum (25ns) Over Samp (15 ns) 600 ns out of FPGA 160 ns

18. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 18 Trigger Output @ 40 MHz ( NRZ encoded)

19. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 19 TRU Card Status ( Layout finalized, Prototypes Nov. 05 ) FPGA 14 octal ADC both sides USB Reconfiguration logic Quad Rocket I/O option 14 * analog OR input connectors Power connector V0- input L0 out 3* L1 out 2*4 serial out RG45 LV regulator Cooling pipe GTL-bus ( address 0) 11 layer board 6 signal layers

20. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 20 Conclusions PHOS modules contain 3584 crystals with preamplifiers FEE and TRU cards are packaged inside closed PHOS modules TRU card –covers 1/8 of one PHOS module (448 crystals) –112 analog Fast OR inputs from surrounding FEE cards –central element is Xilinx Virtex-II Pro FPGA with 112 serial ADC inputs –Level-0 is low-threshold algorithm pre-trigger for Level-1 –Level-1 is high-threshold algorithm with 3 trigger outputs –Oversampling approach for 480 Mb/s LVDS input deserializer First TRU prototype expected November 05

21. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 21 Acknowledgements To Gerd Troeger (Kirchhoff Institut fuer Physik Heidelberg) for the helpful discussions and guidelines during the development of the trigger algorithm

22. Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 22 Trigger-Region-Unit for PHOS Calorimeter H.Muller, A.Oltean, R.Pimenta, D.Rohrich, B. Skaali Thank you!