1. Laboratoire de Physique Corpusculaire - Caen S. Drouet – sdrouet@lpccaen.in2p3.fr FEAST Front-End Asic for Snemo Tracker Journées VLSI–PCB–FPGA–IAOCAO IN2P3 Sébastien Drouet, Laurent Leterrier LPC Caen, ENSICAEN, Université de Caen, CNRS/IN2P3, Caen, France June, 7 th 2011 SNEMO Collaboration Meeting, 10/27/2011

2. S. Drouet – sdrouet@lpccaen.in2p3.fr FEAST OUTLINE 1.Overview 2.Main specifications 3.ASIC Diagrams 4.ASIC Layout 5.Status 6.Conclusion 2

3. S. Drouet – sdrouet@lpccaen.in2p3.fr FEAST 1.Overview A SuperNEMO module (x 20)  5 kg of source ( 82 Se)  Tracker: Drift chamber of 2000 Geiger cells  Calorimeter: 550 PVT scintillators + 8" PMTs Installation of a module for 2014 in LSM. 3

4. S. Drouet – sdrouet@lpccaen.in2p3.fr FEAST 2.Main specifications Technology: 0.35µm CMOS Austriamicrosystem 54 channels corresponding to 18 or 27 geiger cells depending of the configuration 3 types of channel: Anodic, Cathodic or Generic Channel Configurable gain (20/40/60 or 80) for all amplifiers Common configurable thresholds for all discriminators Registers:  Depth of 5 for anodic and 1 for cathodic  Length of 64 bits Time resolution: 12.5ns (48-bit Gray counter @ 80MHz) Output Bus: 16 bits @ 10 MHz (token ring system) Trigger information: 27 bits @ 40 MHz = 675ns (shift registers) Slow-Control: 2 shift registers, one with 255 bits and the other with 193 bits, running @ 10 MHz 3

5. S. Drouet – sdrouet@lpccaen.in2p3.fr FEAST 3.ASIC Diagram 4 GC Readout Data_Out 16bits Anodic Input Anodic or Cathodic Input Anodic Input Cathodic Input Cathodic Input Cathodic Input 54 inputs (6x9) AC CC AC CC AC = Anodic Channel CC = Cathodic Channel GC = Generic Channel, can be configurated in Anodic or Cathodic mode Slow-Control Register (more than 430 bits) Not_Empty_Cathode_Memory Token_Go Data_Reg_Ready Data_Read Token_Back SC_CLK SC_DataIN SC_Load SC_DataOut SC_ChipSelect CommonTestInput Trigger System (27 or 18 bits) Trig_Shift_Out Lock_Trig_Register Trig_Clock Authorized Channels in anodic mode for building Trigger information Trig_Channels CH0 CH1 CH2 CH3 CH4 CH5 Upto CH53 with the same struture of 6 channels CH2 10-bit DACs ‘V LNT ’ & ‘V HNT ’ & ‘V HPT ’ 10-bit DAC ‘V CPT ’ 48-bit Timestamp Counter 80 MHz SC_EnDebug Not_Empty_Anode_Memory SC_ReadMem

6. S. Drouet – sdrouet@lpccaen.in2p3.fr FEAST 3.ASIC Diagram Anodic Channel Diagram 5 V HPT V LNT V HNT Register(4x16bits): 48 bits: TimeStamp 2 bits: Chip_ID 6 bits: Channel_ID 3 bits: Register_ID 1 bit: Mode (A or C) 4 bits: unused Low-pass Amplifier G=20 BW = 2 MHz Comparator Positif Pulse Detector TS Register (Depth 1) Voltage adder OR CommonTestInput Anodic Readout Common to 54 channels Comparator Negatif Pulse Detector Digital_Probe_3 Digital_Probe_4 Data_Out Token_Go Data_Read Token_Back Trig_Channels Band-pass Amplifier G=1/2/3/4 BW = 1.5 MHz Comparator Negatif Pulse Detector V LNT V HNT V HPT OR InhibitionInhibition nEn_ChX TS Register (Depth 2) TS Register (Depth 2) Delay 115µs Trig sequencer Trig Shift Register (27 or 18 bits) Trig_Shift_Out Lock_Trig_Register Trig_Clock Not_Empty_Anode_Memory Analog_Probe_3 Analog_Probe_4 Digital_Probe_2 Data_Reg_Ready 48-bit Counter 80 MHz Select_Offset_ChX Select_Gain_ChX V Offset_AC_1 V Offset_AC_2 nValid_Trig_ChX

7. S. Drouet – sdrouet@lpccaen.in2p3.fr FEAST 3.ASIC Diagram Cathodic Channel Diagram 6 Inhibition nEn_ChX The channel is only dedicated to cathodic signals. The selection of the gain is common to all the cathodic channels Register (4x16bits): 48 bits: Time_Stamp 2 bits: Chip_ID 6 bits: Channel_ID 3 bits: Register_ID 1 bit: Mode (A or C) 4 bits: unused Low-pass amplifier G=20 BW = 2 MHz Comparator Positive pulse Detector TS Register (Depth 1) OR Common to 54 channels Not_Empty_Cathode_Memory Readout Data_Out Token_Go Data_Read Token_Back Data_Reg_Ready 48-bit Counter 80 MHz Band-pass amplifier G=1/2/3/4 BW = 1.5 MHz Sel_CC_Gain V CPT CommonTestInput Cathodic Digital_Probe_1 or Digital_Probe_5 Analog_Probe_1 or Analog_Probe_2 V Offset_CC_1 V Offset_CC_2

8. S. Drouet – sdrouet@lpccaen.in2p3.fr FEAST 3.ASIC Diagram Generic Channel Diagram 7 External Trigger Register (4x16bits): 48 bits: TimeStamp 2 bits: Chip_ID 6 bits: Channel_ID 3 bits: Register_ID 1 bit: Mode (A or C) 4 bits: unused Low-pass Amplifier G=20 BW = 2 MHz Comparator Positif Pulse Detector TS Register (Depth 1) Voltage adder OR CommonTestInput Generic Readout Common to 54 channels Comparator Negatif Pulse Detector Digital_Probe_5 Digital_Probe_4 Data_Out Token_Go Data_Read Token_Back Trig_Channels Band-pass Amplifier G=1/2/3/4 BW = 1.5 MHz Comparator Negatif Pulse Detector V LNT V HNT V HPT OR InhibitionInhibition nEn_ChX TS Register (Depth 2) TS Register (Depth 2) Delay 115µs Trig sequencer Trig Shift Register (27 or 18 bits) Trig_Shift_Out Lock_Trig_Register Trig_Clock Not_Empty_Anode_Memory Analog_Probe_2 Analog_Probe_4 Digital_Probe_2 Data_Reg_Ready 48-bit Counter 80 MHz Select_Offset_Vlnt_ChX Select_Gain_ChX Select_Type_ChX V CPT V Offset_AC_1 V Offset_AC_2 V Offset_CC_1 V Offset_CC_2 nValid_Trig_ChX Not_Empty_Cathode_Memory

9. S. Drouet – sdrouet@lpccaen.in2p3.fr FEAST 4.ASIC Layout 8 1 Register + Readout Slow Control Comparator Band-pass Amplifier Low-pass Amplifier Layout of Cathodic Channel (2170 µm x 230 µm) 5 TS Registers + Readout + Trigger System Slow Control 3 Comparators Band-pass Amplifier Low-pass Amplifier Voltage Adder Layout of Anodic Channel (2170 µm x 401 µm)

10. FEAST 4.ASIC Layout Global Layout 9 Dimension: 5000 µm x 7700 µm (38.5 mm²) 160 pins Layout simulation with ULTRASIM Submission: December 2011 10-bit DACs Amplifiers Registers & Logic for all channels Discriminators Slow-control registers Buffers for analogue probes Counter@80MHz 10-bit DACs S. Drouet – sdrouet@lpccaen.in2p3.fr

11. FEAST 5.ASIC Status Tests already done Consumption: 3.3 V / 270 mA. Slow-control working at 10 MHz. Reading the trigger word at 40 MHz. 16-bit Output Bus working at 10 MHz. Common Test Input.  Digital part OK Tests in progress Characterization of the analog stages To be done: Measuring the time resolution. 10

12. S. Drouet – sdrouet@lpccaen.in2p3.fr FEAST 6.Conclusion Tests réalisés satisfaisants, caractérisation à finir. Intégration de 2 ASICs sur la carte front-end du tracker de SNEMO par nos collègues de l’Université de Manchester. (fin juin 2012). Production et test d’une série de 150 puces pour le prototype de SNEMO (équivalent à environ 8000 voies) pour 2013. 11