1. Architecture and Implementation of the Front-End Electronics of the Time Projection Chambers in the T2K Experiment P. Baron, D. Besin, D. Calvet, C. Coquelet, X. de la Broïse, E. Delagnes, F. Druillole, A. Le Coguie, E. Monmarthe, E. Zonca DSM/IRFU/SEDI, CEA Saclay, France

2. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr2 Tokai to Kamioka (T2K) experiment Main Physics Goal: neutrino oscillation μ disappearance for improved accuracy on  23 e appearance to improve sensitivity to  13 50 kT water

3. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr3 T2K Time-Projection Chambers TPC features Resolution goal: 10% for p < 1 GeV/c Double wall design; inner wall is the field cage Total ~9 m 2 instrumented with 72 Micromegas amplification modules segmented in ~7 mm x ~10 mm pads Custom readout electronics 1 of 3 TPCs shown 1728 pad (36 x 48) Micromegas module 34 cm x 36 cm CalibrationGas systemElectronics; on-line software 1 m 2 m

4. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr4 TPC Readout Challenges Environment Embedded front-end: limited access, need low power No radiation, low magnetic field (0.2 T), Japanese underground facility Highly segmented detector 124.000 channels over 9 m 2 of instrumented area → Massive replication of identical modular building blocks Extreme burstiness of data 124.000 channels; sampling: 12-bit 33 MHz → 50 Tbps → beyond capability of fully digital solution for power budget target Large raw event size but modest average dataflow 50 Tbps during ~15 µs drift time → 90 MBytes Allowable event size for storage: ~250 KBytes → data reduction of ~400 to achieve in real time Spill repetition period: ~3.5 s; Cosmic calibration: 20 Hz max. DAQ average rate: ~250 KBytes × 20 Hz = 5 MByte/s → commercial computers and networking techniques

5. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr5 Logical Read-Out Flow Architecture principles Custom front-end ASIC; analog memory (Switch Capacitor Array) ADC + digital buffer mounted close to the detector Multiple optical fibers send data to off-detector concentrator cards Interface to common DAQ via standard gigabit Ethernet network Pre-amp and shapers Samplers and analog memory buffers Analog to digital conversion Digital buffer – zero-suppression Data concentrator Clock/Trigger fanout ~124.000 channels 1728 ASICs On-detector 72 Optical fibers ~4 Tbaud*/s peak *1 baud = 12 bit ~2 ms retention max. 34 Gbaud/s peak 400 Gbit/s peak ~1-10 Gbit/s averaged Shared DAQ ~0.1-1 Gbit/s 432 Front End Cards 12 (18) Data Concentrator Cards 72 Front-End Mezzanines cards Off-detector Global Clock/Trigger Gigabit Ethernet

6. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr6 Architecture Implementation 3 TPCs 1 m 2,5 m Network TCP/IP PC Linux DCCs Private Ethernet Gigabit Ethernet DAQ control Detector B Detector A Global trigger 1 of 6 TPC end-plates (12-modules) Outside magnetInside magnet 2 of 12 (or 18) Data Concentrator Cards x 6 12 duplex Optical fibres 1 of 72 modules Front End Mezzanine Card (FEM) 288 channel Front End Card (FEC) 1728 pad Micromegas plane Slow control network Optical fiber to/from DCC Low voltage Power supply 1 of 1728 Front-End ASIC “AFTER” 72 channel x 511 time buckets Switched capacitor array

7. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr7 ASIC “AFTER” Functional Diagram AFTER 511 cells SCAFILTER 100ns<tpeak<2us CSA 1 channel x72(76) 76 to 1 BUFFER SCA MANAGER SLOW CONTROL Serial Interface W / R Mode CK ADC TEST In Test 120fC<Cf<600fC Power SupplyReference VoltageReference Current Asic Spy Mode CSA;CR;SCAin (N°1) Power On Reset Design features 72 channels x 511 analog memory cells; F write : 1-50 MHz; F read : 20 MHz 4 Charge Ranges (120 fC; 240 fC; 360 fC & 600 fC) Supports positive or negative input signals 16 Peaking Time Values (100 ns to 2 µs) MIP/noise: 100; I.N.L: 1% [0;3 Mips], 5% [3-10 Mips] SCA readout time: 2 ms (at 20 MHz) – 500 Hz max. event rate Asic For Tpc Electronic Read-out

8. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr8 The AFTER chip Design facts 0.35 µm CMOS - 500.000 transistors 7.8 x 7.4 mm die – 160-pin 0.65 mm pitch LQFP single 3.3V supply - 8 mW/channel Performance Integral non-linearity < 1.2% full range ENC: 350 electrons (without load) Sampling skew (all time-bins of one channel): 700 ps rms Stored charge degradation after 2 ms retention: 0.18 LSB

9. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr9 AFTER chip test and production Production of the AFTER chip 5300 chip produced; 4750 OK; Yield: 89% 1800 chips delivered to T2K (TPC + FGD + monitoring chamber) LABVIEW Test Software Protection 1 Protection 2No Protection AFTER Test Card Test bench AFTER test card served as pre-prototype of Front-End Card Xilinx Virtex 2 Pro eval. kit as pre-prototype of FEM board for readout DAQ and Analysis with Ethernet PC and LabView

10. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr10 Front-End Card (FEC) Features All design concepts validated on AFTER test board 1 FEC reads out 288 channels – 6 layer PCB Consumption: 1 A – 4 W → 2:3 of ~500 FECs ordered now produced and validated Quad-channel 12-bit ADC AD9229 Passive protection Circuits 4 AFTER chips 3.3V regulators Silicon ID chip V - I –T monitor +4V input Four dual row 80-pin 1.27 mm pitch connectors to detector Pulser Clock fanout PhotoMos relay 80-pin connector to FEM

11. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr11 Main functions Drive 6 FECs and aggregate data produced (1728 channels, 5.7 Gbps) Buffer one event (raw data), i.e. ~10 Mbit Deliver data to DCC upon request: raw data or zero-suppressed (one programmable threshold per channel) Configuration and slow control, voltage, current, temperature monitoring Front-end Mezzanine (FEM) card ZBT SRAM 2 Gbps optical transceiver CANbus slow control (RJ45) FPGA µC FEC#1 Voltage regulators JTAG Power In Connector FEC#0 BuffersFEC#2 FEC#3FEC#4FEC#5

12. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr12 Detector Module Read-out Electronics 72-channel ASIC Quad-channel ADC digital Front-end Mezzanine card (FEM) Optical Transceiver FPGA 80-pin connector 288-channel analog Front-End Card (FEC) 1728-pad detector plane Slow-control Network - CANbus Fiber to DCC Low voltage power Materializing the concept 3 year development of ~6 equivalent persons from ASIC specifications to working readout of one detector module

13. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr13 Backend Electronics Current Status 6-optical ports DCC still under development by collaborators → Interim solution for a 4-optical ports DCC: commercial Xilinx Virtex 4 ML405 board custom card with 3 optical transceivers + new clock distribution Transceiver Board Clock Board Connector Board Cell Phone Coaxial Cables

14. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr14 FEC-FEM-DCC DAQ Performance FEM#0FEM#1FEM#2FEM#3 ML405 DCC Ethernet UDP/IP PC Data sink Main results Maximum rate (44 Hz) close to upper limit imposed by FEMs (~50 Hz) Event acquisition time = 23 ms + event size x 5 MB/s Limitation: PPC405 (300 MHz) I/O over 100 MHz PLB (V4.6 → Improvements with DMA’s studied but system already within specs Scalability with number of DCC’s to be studied – but total dataflow ~5 MB/s 0 10 20 30 40 50 60 70 80 064128192256 DCC Event Size (KB) Event readout time (ms) Time budget DCC Event size = ~2 bytes x nb_pads_hit_in_4_modules x (nb_time_bins_overthreshold+14) Expected event size

15. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr15 Integration of TPC#0 at Triumf

16. RT2009 – Beijing 10-15 May 2009calvet@hep.saclay.cea.fr16 Summary What? A 124.000 channel readout system for the 3 TPCs of the T2K experiment How? 72-channel ASICs based on a 511 time-bucket switched capacitor array Six Front-End Cards + 1 Front-end Mezzanine Card at the back of each of the 72 Micromegas detectors Propose interim solution for back-end Data Concentrator Cards: commercial Xilinx Virtex 4 evaluation board + PC and standard Ethernet networking Principal merit? High density, low power: ~16 mW/channel (2 kW for 124.000 ch.); ~3 €/ch. Status and Future Work 1 fully equipped TPC extensively tested; 2 nd TPC: June ’09; 3 rd TPC: Sept. ’09 → 3 TPCs equipped, installed and commissioned at J-PARC by end ‘09