Test complexity of TED operations Use canonical property of TED for - Software Verification - Algorithm Equivalence check - High Level Synthesis M ac iej Ciesielski ECE Department University of Massachusetts, Amherst ECE Project Ideas

 Compact, canonical representation for arithmetic functions (F: Int  Int )  Treat discrete function as continuous (polynomial)  Taylor Expansion (around x=0): F(x) = F(0) + x F’(0) + ½ x 2 F’’(0) + …  Notation F(x=0) 0-child F’(x=0) 1-child ½ F’’(x=0) 2-child ====== etc. F(x) = 0-child + x (1-child) + x 2 (2-child) + … Taylor Expansion Diagram (TED) x F(0) F’(0) F’’(0)/2 … F(x)

TED – a few Examples (A+B)(A+2C) 1 0 B C A B x0 x1 x2 x x0 x1 x X 2 = (8x 3 + 4x 2 + 2x 1 + x 0 ) 2 TED: not a BDD, not a *BMD, not a decision diagram A,B,C: arbitrary word width X decomposed in bits

TED: Composition & Manipulation  Analogous to BDD and *BMD, TED:  Requires an ordering of variables  Has to be reduced  Has to be normalized  Reduced ordered normalized TED is canonical  Composition of TED:  f = g + h; APPLY(+, g, h)  f = g * h; APPLY(*, g, h)  f = g – h; APPLY(+, g, APPLY(*, -1, h))

Verification of Algorithmic Specifications x x x x FAB1 FAB2 FAB3 A0 A1 A3 A2 B0 B1 B2 B3 FFT(A) FFT(B) IFFT0 IFFT1 IFFT3 IFFT2 InvFFT(FAB) A[0:3] B[0:3] C0 C1 C2 C3 Conv(A,B) Use TED to prove equivalence: IFFT i =C i  

Isomorphic TEDs: IFFT(i)  Conv(i) 0 4 A0 A2 A1 A3 B1 B3 B2 B0 IFFT0 = C0 = 4{ A0*B0 + A1*B3 + A2*B2 + A3*B1}

TED for High Level Synthesis Trends and problems in industry Design Flow High level synthesis –Prior art –Problems with prior art New canonical method –TED’s

Need for abstraction International Technology Roadmap for Semiconductors (ITRS 2001) Report highlights –Moore’s law will be valid for 10 more years 10 billion transistors 10 Ghz 30nm technology –Enormous complexity can only handled by targeting at high levels of design

Design Flow RTL Description Logic Synthesis Floorplanning Placement Routing Tape-out Circuit Extraction Pre-Layout Simulation Post-Layout Simulation Structural Physical Behavioral Design Iteration HDL High-level Synthesis

High Level Synthesis Architectural solution minimized for given objective, constraints Architecture Specification (HDL)... Data Flow Graph Objectives, constraints: Power Area Latency

High Level Synthesis Example Inputs: A, B, C, D Output: F ……… assign F = A*B + A*C ………. Common Data Flow Graph (DFG) Architecture 2: 1 Mult, 1 Add, L = 3 cycles Cycle 1 Cycle 2 x + x Cycle 3 A CA B F Architecture 1: 2 Mult, 1 Add, L = 2 cycles xx + Cycle 1 Cycle 2 ACAB F

Alternative solution The data flows are derived directly from user’s specification There is a need for a higher level of synthesis: Transformation A*B + A*C = A*(B+C) Abstract level synthesis should provide Canonical representation Basis for optimal solutions for different objectives To derive alternative solutions, need new Data Flow Graph user must rewrite the initial specification (HDL) replace (A B + A C) by A (B + C) Alternative architecture: 1 Mult, 1 Add, L = 2 cycles + x Cycle 1 Cycle 2 C A B F

High Level Synthesis F = A*B + A*C Area Latency xx + Specification Data flow graph xx + Cycle 1 Cycle 2 Cycle 1 Cycle 2 x + x Cycle 3 AB ABAC AC Algorithms Scheduling Allocation Resource binding

Current HL Transformation Methods Ad-hoc methods (algebraic) –Commutativity: A + B = B + A –Associativity: A + (B +C) = (A + B) + C –Distributivity: A * (B +C) = (A * B) + (A * C) Term rewriting, etc. Tools –Matlab, Maple –Mathematica Problems: –not canonical –cannot scale with design size –require manual intervention

Taylor Expansion Diagrams Features of TED –Canonical, minimal, normalized –Compact (linear for polynomials) –Represents word-level blocks and Boolean logic Applications –Equivalence checking, RTL verification –Symbolic simulation (representation) –Algorithm verification NEW: Application to Behavioral Synthesis

Application to Behavioral Synthesis Given an algorithm, derive several implementations using common (canonical) structure of TED F1 = AB + AC  +  A BC F2 = A (B + C)  + ABC A B C 0 1 AB + AC HLD

Alternative Architecture F = A*(B+C) Area Specification Data flow graph + x Cycle 1 Cycle 2 + x C A B