1. ECE 667 - Synthesis & Verification - Lecture 10 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Binary Decision Diagrams (BDD)

2. ECE 667 - Synthesis & Verification - Lecture 10 2 Outline Background – –Canonical representations BDD’s – –Reduction rules – –Construction of BDD’s – –Logic manipulation of BDD’s – –Application to verification and SAT Reading: read one of the BDD tutorials available on class web site – –Anderson, or – –Somenzi

3. ECE 667 - Synthesis & Verification - Lecture 10 3 Common Representations Boolean functions ( f : B  B ) – –Truth table, Karnaugh map – –SoP, PoS, ESoP – –Reed-Muller expansions (XOR-based) – –Decision diagrams (BDD, ZDD, etc.) Each minimal, canonical representation is characterized by – –Decomposition type Shannon, Davio, moment decomposition, Taylor exp., etc. – –Reduction rules Redundant nodes, isomorphic sub-graphs, etc. – –Composition method (“Apply”, compose rule) What they represent – –Boolean functions (f : B  B) – –Arithmetic functions (f : B  Int ) – –Algebraic expressions (f : Int  Int )

4. ECE 667 - Synthesis & Verification - Lecture 10 4 Binary Decision Diagrams ( BDD ) Based on recursive Shannon expansion f = x f x + x’ f x’ Compact data structure for Boolean logic – –can represents sets of objects (states) encoded as Boolean functions Canonical representation – –reduced ordered BDDs (ROBDD) are canonical – –essential for verification

5. ECE 667 - Synthesis & Verification - Lecture 10 5 ROBDD’s Directed acyclic graph (DAG) one root node, two terminals 0, 1 each node, two children, and a variable Shannon co-factoring tree, except reduced and ordered (ROBDD) – –Reduced: any node with two identical children is removed two nodes with isomorphic BDD’s are merged – –Ordered: Co-factoring variables (splitting variables) always follow the same order along all paths x i 1 < x i 2 < x i 3 < … < x i n

6. ECE 667 - Synthesis & Verification - Lecture 10 6 Example Two different orderings, same function. a bb cc d 0 1 c+bd b root node c+d c d f = ab+a’c+bc’d a c d b 01 c+bd d+b b 1 0

7. ECE 667 - Synthesis & Verification - Lecture 10 7 ROBDD Ordered BDD (OBDD) Input variables are ordered - each path from root to sink visits nodes with labels (variables) in ascending order. a cc b 0 1 ordered order = a,c,b Reduced Ordered BDD (ROBDD) - reduction rules: 1.if the two children of a node are the same, the node is eliminated: f = vf + vf 2.if two nodes have isomorphic graphs, they are replaced by one of them These two rules make it so that each node represents a distinct logic function. a b c c 0 1 not ordered b

8. ECE 667 - Synthesis & Verification - Lecture 10 8 Efficient Implementation of BDD’s BDDs is a compressed Shannon co-factoring tree: f = v f v + v f v leafs are constants “0” and “1” Three components make ROBDDs canonical (Proof: Bryant 1986): – –unique nodes for constant “0” and “1” – –identical order of case splitting variables along each paths – –hash table that ensures: (node(f v ) = node(g v ))  (node(f v ) = node(g v ))  node(f) = node(g) – –provides recursive argument that node(f) is unique when using the unique hash-table v 0 1 f fvfv fvfv

9. ECE 667 - Synthesis & Verification - Lecture 10 9 Onset is Given by all Paths to “1” Notes: By tracing paths to the 1 node, we get a cover of pair wise disjoint cubes. The power of the BDD representation is that it does not explicitly enumerate all paths; rather it represents paths by a graph whose size is measures by its nodes and not paths. A DAG can represent an exponential number of paths with a linear number of nodes. BDDs can be used to efficiently represent sets – –interpret elements of the onset as elements of the set – –f is called the characteristic function of that set F = b’+a’c’ = ab’+a’cb’+a’c’ all paths to the 1 node a c b 0 1 1 0 1 1 0 0 f f a = b’ f a = cb’+c’

10. ECE 667 - Synthesis & Verification - Lecture 10 10 Implementation Variables are totally ordered: If v < w then v occurs “higher” up in the ROBDD Top variable of a function f is a variable associated with its root node. Example: f = ab + a’bc + a’bc’. Order is (a < b < c). f a = b, f  a = b a b 01 f b is top variable of f b 01 f reduced f does not depend on a, since f a = f  a. Each node is written as a triple: f = (v,g,h) where g = f v and h = f  v. We read this triple as: f = if v then g else h = ite (v,g,h) = vg+v ’ h v f 01 h g 10 f v g h mux v is top variable of f

11. ECE 667 - Synthesis & Verification - Lecture 10 11 BDD Construction Reduced Ordered BDDReduced Ordered BDD 1 edge 0 edge a b c f 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 Truth table f = ac + bc Decision tree 1 0 001010 a b c b ccc f

12. ECE 667 - Synthesis & Verification - Lecture 10 12 BDD Reduction Rules -1 Eliminate redundant nodesEliminate redundant nodes (with both edges pointing to same node) f = f a g(b) + f a’ g(b) = g(b) (f a + f a’ = 1) b g a b f g

13. ECE 667 - Synthesis & Verification - Lecture 10 13 BDD Reduction Rules -2 Merge duplicate nodes (isomorphic subgraphs)Merge duplicate nodes (isomorphic subgraphs) Nodes must be unique f 1 = f a’ g(b) + f a h(c) = f 2 f = f 1 = f 2 aa bc h g f1f1 f2f2 a bc g h f

14. ECE 667 - Synthesis & Verification - Lecture 10 14 BDD Construction – cont’d 10 a b c b ccc ff 10 a b c b c 10 a b c f = (a+b)c 2. Merge duplicate nodes 1. Merge terminal nodes 3. Remove redundant nodes

15. ECE 667 - Synthesis & Verification - Lecture 10 15 APPLY Operator Useful in constructing BDD for arbitrary Boolean logicUseful in constructing BDD for arbitrary Boolean logic Any logic operation can be expressed using Apply (ITE)Any logic operation can be expressed using Apply (ITE) Efficient algorithms, work directly on BDD graphsEfficient algorithms, work directly on BDD graphs Apply: F G, any Boolean operationApply: F G, any Boolean operation (AND, OR, XOR,  ) =  F G 0 1 0 1 0 1 F G 

16. ECE 667 - Synthesis & Verification - Lecture 10 16 Logic Manipulation using BDDs Useful operatorsUseful operators –Complement ¬ F = F’ (switch the terminal nodes) –Restrict: F| x=b = F(x=b) where b = const ¬ 1 0 0 1 FF’ 0 1 F(x,y) x=b 0 1 F(y) Restrict

17. ECE 667 - Synthesis & Verification - Lecture 10 17 Useful BDD Operators – Apply Operation Basic operator for efficient BDD manipulation (structural)Basic operator for efficient BDD manipulation (structural) Based on recursive Shannon expansionBased on recursive Shannon expansion F OP G = x (F x OP G x ) + x’(F x’ OP G x’ ) F OP G = x (F x OP G x ) + x’(F x’ OP G x’ ) where OP = OR, AND, XOR, etc

18. ECE 667 - Synthesis & Verification - Lecture 10 18 Apply Operation (cont’d) Apply: F GApply: F G where stands for any Boolean operator (AND, OR, XOR,  )   =  F G 0 1 0 1 0 1 F G  Any logic operation can be expressed using only Restrict and Apply Efficient algorithms, work directly on BDDs

19. ECE 667 - Synthesis & Verification - Lecture 10 19 Apply Operation - AND 10 a c ac a AND c 10 a 2 c 10 3 0.3 2.3 a c 1.3 1.11.0 AND = =

20. ECE 667 - Synthesis & Verification - Lecture 10 20 Apply Operation - OR OR ac 10 a c 4 5 bc 10 b c 6 7 = = 10 a b c f = ac+bc c 4+6 0+0 a 7+5 1 0+6 b 6+5 0+5 0 0+7

21. ECE 667 - Synthesis & Verification - Lecture 10 21 Application to Verification Equivalence Checking of combinational circuitsEquivalence Checking of combinational circuits Canonicity property of BDDs:Canonicity property of BDDs: –if F and G are equivalent, their BDDs are identical (for the same ordering of variables ) 10 a b c F = a’bc + abc +ab’c G = ac +bc 10 a b c 

22. ECE 667 - Synthesis & Verification - Lecture 10 22 Application to SAT Functional test generationFunctional test generation –SAT, Boolean satisfiability analysis –to test for H = 1 (0), find a path in the BDD to terminal 1 (0) –the path, expressed in function variables, gives a satisfying solution (test vector) ab ab’c H 0 1 a b c Problem: size explosion

23. ECE 667 - Synthesis & Verification - Lecture 10 23 Efficient Implementation of BDD’s Unique Table: avoids duplication of existing nodes – –Hash-Table: hash-function(key) = value – –identical to the use of a hash-table in AND/INVERTER circuits Computed Table: avoids re-computation of existing results hash value of key collision chain hash value of key No collision chain