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1 High-Level Design Verification using Taylor Expansion Diagrams: First Results Priyank Kalla ECE Department University of Utah Maciej Ciesielski ECE Department.

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Presentation on theme: "1 High-Level Design Verification using Taylor Expansion Diagrams: First Results Priyank Kalla ECE Department University of Utah Maciej Ciesielski ECE Department."— Presentation transcript:

1 1 High-Level Design Verification using Taylor Expansion Diagrams: First Results Priyank Kalla ECE Department University of Utah Maciej Ciesielski ECE Department. Univ. of Massachusetts Emmanuel Boutillon, Eric Martin LESTER, Universite de Britagne Sud Lorient, France

2 2  Compact, canonical representation for arithmetic functions (F: Int  Int )  Treat discrete function as continuous (polynomial)  Taylor Expansion (around x=0): F(x) = F(0) + x F’(0) + ½ x 2 F’’(0) + …  Notation F(x=0) 0-child - - - - - - F’(x=0) 1-child ---------- ½ F’’(x=0) 2-child ====== etc. F(x) = 0-child + x (1-child) + x 2 (2-child) + … Taylor Expansion Diagram (TED) x F(0) F’(0) F’’(0)/2 … F(x)

3 3 TED – a few Examples (A+B)(A+2C) 1 0 B C A B 1 2 1 x0 x1 x2 x3 2 4 1 0 1 x0 x1 x2 1 1 1 4 4 8 16 64 1 1 X 2 = (8x 3 + 4x 2 + 2x 1 + x 0 ) 2 TED: not a BDD, not a *BMD, not a decision diagram A,B,C: arbitrary word width X decomposed in bits

4 4 TED: Composition & Manipulation  Analogous to BDD and *BMD, TED:  Requires an ordering of variables  Has to be reduced  Has to be normalized  Reduced ordered normalized TED is canonical  Composition of TED:  f = g + h; APPLY(+, g, h)  f = g * h; APPLY(*, g, h)  f = g – h; APPLY(+, g, APPLY(*, -1, h))

5 5 TED: Applications and First Results  TED can represent multivariate polynomials  Possible applications  Discrete functions  polynomials  RTL transformations: A*B + A*C = A*(B+C)  Algorithm specification and verifications  Experimental results

6 6 Verification Experiments: RTL Transformations A*C + B*C + A*D + B*D = (A+B)*(C+D) (arbitrary word-width) Word Size(n) *BMDTEDNorm. TED SizeTimeSizeTimeSizeTime 84181.5s61s6 1611662.8s61s6 2422166s61s6 32280814s61s6

7 7 Array Processing 16x16 PE Array Sum PE FIFOs B[ j ] A[ i ] - + Previous PE Computation Sum of Differences B[ j ] A[ i ] - + Previous PE Computation Sum of Differences Of squares 2 2

8 8 Array Processing PE Computation: A[ i ] – B[ j ], 8-bit vectors Effect of array size Size (# nodes)Time [s]

9 9 Verification Experiments: Array Processing PE Computation: A[ i ] – B[ j ], 8-bit vectors Effect of array size 22 Size ( nodes)Time [s]    = out of memory

10 10 Applications to RTL Verification  Equivalence checking with TEDs  interfacing arithmetic and Boolean domains A B s2s2 0101 F2F2 bkbk akak * * - D B A s1s1 1010 F1F1 D akak bkbk > + * - F 1 = s 1 (A+B)(A-B) + (1-s 1 )D s 1 = (a k > b k ) = a k (1-b k ) F 2 = (1-s 2 ) (A 2 -B 2 ) + s 2 D s 2 = a k ’  b k = 1 - a k + a k b k A = [a n-1, …,a k,…,a 0 ] = [A hi,a k,A lo ], B = [b n-1, …,b k,…,b 0 ] = [B hi,b k,B lo ] A = 2 (k+1) A hi + 2 k a k + A lo B = 2 (k+1) B hi + 2 k b k + B lo

11 11 RTL Verification – cont’d. F 1 = s 1 (A+B)(A-B) + (1-s 1 )D A = [A hi, a k, A lo ] B = [B hi, b k, B lo ] s 1 = (a k > b k ) = a k (1-b k ) 1 akak 1 A hi D akak bkbk bkbk B hi A lo B lo 2k2k 1 2 2k+2 2 k+2 -2 k+2 -2 2k+2 F 1 = F 2 A lo 1 2 k+1 2k2k 0

12 12 Algebraic-Boolean Interface Size of TEDs vs. Boolean Logic Vary k = size of Boolean logic Size (nodes) Time [s]  

13 13 Verification of Algorithmic Specifications x x x x FAB1 FAB2 FAB3 A0 A1 A3 A2 B0 B1 B2 B3 FFT(A) FFT(B) IFFT0 IFFT1 IFFT3 IFFT2 InvFFT(FAB) A[0:3] B[0:3] C0 C1 C2 C3 Conv(A,B)

14 14 Isomorphic TEDs: IFFT(i)  Conv(i) 0 4 A0 A2 A1 A3 B1 B3 B2 B0 IFFT0 = C0 = 4{ A0*B0 + A1*B3 + A2*B2 + A3*B1}

15 15 Applications to Galois Field Computations  Assume Galois Field GF[8], let  be primitive element of GF(8)  Q[XY] = (  X +  Y)(  X +  Y)  R[XY] =  X +  Y  Q[XY] = R[XY] (isomorphic TEDs) X Y 0 1  2  4 X Y 0 1  1  3 * = X Y 0 1  3  0 X Y 1  3  2 +  4  1 = 0 =  0  4  3 = 4321 0322 0

16 16 Conclusions and Future Work  Limitations, RTL:  Increase in Boolean logic degrades performance  Internal fanouts a problem  Cannot break outputs into subfields  Applications:  RTL, behavioral, algorithmic levels  Specification and equivalence checking  Applicable to varied computational domains: integer, binary, complex, Galois Field, etc.  DSP, error correction coding, cryptography….  Potential application: Architectural Synthesis?

17 17 Properties of TED  Canonical  Compact  Linear for polynomials of arbitrary degree  TED for X k, k = const, with n bits, has k(n-1)+1 nodes  *BMD is polynomial in n  Can contain symbolic, word-level, and Boolean variables  It is not a Decision Diagram n = 4, k = 2 1 x0 x1 x2 x3 2 4 1 0 1 x0 x1 x2 1 1 1 4 4 8 16 64 1 1 X 2 = (8x 3 + 4x 2 + 2x 1 + x 0 ) 2

18 18 Verification Experiments: Array Processing PE Computation: A[ i ] – B[ j ] A[ i ], B[ j ]: 8-bit vectors Array Size(n) *BMDTEDNorm. TED SizeTimeSizeTimeSizeTime 4 x 4663.1s111s101s 6 x 6983.4s151.5s141.5s 8 x 81303.5s191.5s182s 16 x 162589s352s343.8s

19 19 Verification Experiments: Array Processing PE Computation: A[ i ] – B[ j ] A[ i ], B[ j ]: 8-bit vectors Array Size(n) *BMDTEDNorm. TED SizeTimeSizeTimeSizeTime 4 x 41233s111.2s101.2s 8x86842112s191.5s181.6s 16x16Out of memory357s348.8s 2 2

20 20 Algebraic-Boolean Interface Size of TEDs vs. Boolean Logic Vary k = size of Boolean logic Bits Size(k) *BMDTEDNorm. TED SizeTimeSizeTimeSizeTime 44620107s78324s19444s 1215k87s517413s99874s 1623.9k249s22.3k94s4454104s 18-- > 12hrs 67.9K22mins 12.8 K 29mins 20-->12hrs-->12hrs-->12hrs


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